61 lines
1.3 KiB
VHDL
61 lines
1.3 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY AdderTest IS
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END AdderTest;
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ARCHITECTURE behavior OF AdderTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT CarryLookAhead
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PORT(
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X : IN std_logic_vector(47 downto 0);
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Y : IN std_logic_vector(47 downto 0);
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OP : IN std_logic;
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RESULT : OUT std_logic_vector(47 downto 0);
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OVERFLOW : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(47 downto 0) := (others => '0');
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signal Y : std_logic_vector(47 downto 0) := (others => '0');
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signal OP : std_logic := '0';
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--Outputs
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signal RESULT : std_logic_vector(47 downto 0);
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signal OVERFLOW : std_logic;
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: CarryLookAhead PORT MAP (
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X => X,
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Y => Y,
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OP => OP,
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RESULT => RESULT,
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OVERFLOW => OVERFLOW
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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--test
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wait for clock_period;
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end process;
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END;
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