25 lines
1.2 KiB
Plaintext
25 lines
1.2 KiB
Plaintext
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj work.AddSubTest
|
|
ISim P.20131013 (signature 0xfbc00daa)
|
|
Number of CPUs detected in this system: 4
|
|
Turning on mult-threading, number of parallel sub-compilation jobs: 8
|
|
Determining compilation order of HDL files
|
|
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
|
|
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
|
|
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSubTest.vhd" into library work
|
|
Starting static elaboration
|
|
Completed static elaboration
|
|
Fuse Memory Usage: 94376 KB
|
|
Fuse CPU Usage: 1040 ms
|
|
Compiling package standard
|
|
Compiling package std_logic_1164
|
|
Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
|
|
Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
|
|
Compiling architecture behavior of entity addsubtest
|
|
Time Resolution for simulation is 1ps.
|
|
Waiting for 1 sub-compilation(s) to finish...
|
|
Compiled 7 VHDL Units
|
|
Built simulation executable /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe
|
|
Fuse Memory Usage: 658004 KB
|
|
Fuse CPU Usage: 1060 ms
|
|
GCC CPU Usage: 210 ms
|