2019-08-29 16:38:19 +02:00
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj work.AddSubTest
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ISim P.20131013 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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2019-08-24 14:39:01 +02:00
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Determining compilation order of HDL files
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2019-08-29 16:38:19 +02:00
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSubTest.vhd" into library work
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2019-08-24 14:39:01 +02:00
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Starting static elaboration
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Completed static elaboration
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2019-08-29 16:38:19 +02:00
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Fuse Memory Usage: 94376 KB
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Fuse CPU Usage: 1040 ms
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2019-08-24 14:39:01 +02:00
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Compiling package standard
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Compiling package std_logic_1164
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2019-08-29 16:38:19 +02:00
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Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
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Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
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Compiling architecture behavior of entity addsubtest
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2019-08-24 14:39:01 +02:00
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Time Resolution for simulation is 1ps.
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2019-08-29 16:38:19 +02:00
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 7 VHDL Units
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Built simulation executable /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe
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Fuse Memory Usage: 658004 KB
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Fuse CPU Usage: 1060 ms
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GCC CPU Usage: 210 ms
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