112 lines
2.8 KiB
VHDL
112 lines
2.8 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY NormalizerTest IS
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END NormalizerTest;
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ARCHITECTURE behavior OF NormalizerTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Normalizer
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PORT(
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SIGN : IN std_logic;
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EXP : IN std_logic_vector(7 downto 0);
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MANT : IN std_logic_vector(47 downto 0);
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SUM_OVERFLOW : IN std_logic;
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IEEE_754_SUM : OUT std_logic_vector(31 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal SIGN : std_logic := '0';
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signal EXP : std_logic_vector(7 downto 0) := (others => '0');
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signal MANT : std_logic_vector(47 downto 0) := (others => '0');
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signal SUM_OVERFLOW : std_logic := '0';
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--Outputs
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signal IEEE_754_SUM : std_logic_vector(31 downto 0);
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constant clock_period : time := 10 ns;
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signal clock : std_logic;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Normalizer PORT MAP (
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SIGN => SIGN,
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EXP => EXP,
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MANT => MANT,
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SUM_OVERFLOW => SUM_OVERFLOW,
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IEEE_754_SUM => IEEE_754_SUM
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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SIGN <= '1';
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EXP <= "10010100";
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MANT <= "100101010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '1';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "10010100";
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MANT <= "000000000000000000000000000000000000000000000000";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "00000010";
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MANT <= "000000010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "11111110";
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MANT <= "111111111111111111111111111111111111111111111111";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "11111110";
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MANT <= "111111111111111111111111111111111111111111111111";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "11111111";
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MANT <= "100101010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "11111111";
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MANT <= "100101010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '1';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "11111111";
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MANT <= "000000000000001001000001111101010000001000110001";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "00000001";
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MANT <= "010101010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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SIGN <= '1';
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EXP <= "00000000";
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MANT <= "100101010001001001000001111101010000001000110001";
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SUM_OVERFLOW <= '0';
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wait for clock_period;
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end process;
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END;
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