53 lines
961 B
VHDL
53 lines
961 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity ZeroCheck is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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IS_ZERO : out std_logic
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);
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end ZeroCheck;
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architecture ZeroCheckArch of ZeroCheck is
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component EqualCheck is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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IS_EQUAL : out std_logic
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);
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end component;
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signal S_SIGN : std_logic;
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signal Y_SIGN : std_logic;
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signal X_ABS : std_logic_vector(30 downto 0);
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signal Y_ABS : std_logic_vector(30 downto 0);
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signal IS_SAME_ABS_VALUE : std_logic;
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signal IS_SAME_SIGN : std_logic;
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begin
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S_SIGN <= X(31);
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Y_SIGN <= Y(31);
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X_ABS <= X(30 downto 0);
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Y_ABS <= Y(30 downto 0);
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IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
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ABS_CHECK : EqualCheck
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generic map ( BITCOUNT => 31 )
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port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);
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IS_ZERO <= (not IS_SAME_SIGN) and IS_SAME_ABS_VALUE;
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end ZeroCheckArch;
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