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Completato modulo TwoComplement

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This commit is contained in:
Giulio
2019-08-29 15:12:25 +02:00
parent 8b08af2782
commit 12f2e36d7c
166 changed files with 1038 additions and 6113 deletions
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42
Comparator.vhd
View File

@@ -3,31 +3,43 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is entity Comparator is
generic( BITCOUNT : integer := 8 ); generic( BITCOUNT : integer := 8 );
port( port(
xT, yT: in std_logic_vector((BITCOUNT-1) downto 0); X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic NEED_SWAP : out std_logic
); );
end Comparator; end Comparator;
architecture ComparatorArch of Comparator is architecture ComparatorArch of Comparator is
signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
begin
xGTy <= xT and (not yT);
yGTx <= (not xT) and yT;
needSwap_compute: process (xGTy, yGTx) signal X_GT_Y : std_logic_vector((BITCOUNT-1) downto 0);
variable SW: std_logic; signal Y_GT_X : std_logic_vector((BITCOUNT-1) downto 0);
variable K: std_logic;
begin begin
SW := '0';
K := '1'; X_GT_Y <= X_MANT and (not Y_MANT);
Y_GT_X <= (not X_MANT) and Y_MANT;
NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
variable SWAP : std_logic;
variable SWAP_CARRY : std_logic;
begin
SWAP := '0';
SWAP_CARRY := '1';
for i in (BITCOUNT-1) downto 0 loop for i in (BITCOUNT-1) downto 0 loop
SW := SW or ((not(xGTy(i)) and yGTx(i)) and K); SWAP := SWAP or ((not(X_GT_Y(i)) and Y_GT_X(i)) and SWAP_CARRY);
K := K and (not(xGTy(i) and not(yGTx(i)))); SWAP_CARRY := SWAP_CARRY and (not(X_GT_Y(i) and not(Y_GT_X(i))));
end loop; end loop;
needSwap <= SW;
NEED_SWAP <= SWAP;
end process; end process;
end ComparatorArch; end ComparatorArch;

43
IEEE754Adder.xise
View File

@@ -66,23 +66,25 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
</file> </file>
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="FullAdder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
</file> </file>
<file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
</file>
</files> </files>
<properties> <properties>
@@ -203,9 +205,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FullAdder|FullAdderArch" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TwoComplement|TwoComplementArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="FullAdder.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="TwoComplement.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FullAdder" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/TwoComplement" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -274,7 +276,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="FullAdder" xil_pn:valueState="default"/> <property xil_pn:name="Output File Name" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -289,10 +291,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="FullAdder_map.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TwoComplement_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="FullAdder_timesim.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TwoComplement_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FullAdder_synthesis.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TwoComplement_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FullAdder_translate.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TwoComplement_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -301,6 +303,7 @@
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -316,7 +319,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="FullAdder" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -340,8 +343,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/FullAdderTest" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TwoComplementTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -360,7 +363,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -415,7 +418,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|FullAdderTest|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

33
NaNCheck.vhd
View File

@@ -2,37 +2,44 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity NaNCheck is entity NaNCheck is
port( port(
X, Y : in std_logic_vector(31 downto 0); X, Y : in std_logic_vector(31 downto 0);
isNan: out std_logic IS_NAN : out std_logic
); );
end NaNCheck; end NaNCheck;
architecture NaNCheckArch of NaNCheck is architecture NaNCheckArch of NaNCheck is
component TypeCheck is component TypeCheck is
port( port(
N : in std_logic_vector(31 downto 0); N : in std_logic_vector(31 downto 0);
NaN, INF: out std_logic NAN, INF : out std_logic
); );
end component; end component;
signal xNan: std_logic; signal X_NAN : std_logic;
signal xInf: std_logic; signal X_INF : std_logic;
signal xSign: std_logic; signal X_SIGN : std_logic;
signal yNan: std_logic; signal Y_NAN : std_logic;
signal yInf: std_logic; signal Y_INF : std_logic;
signal ySign: std_logic; signal Y_SIGN : std_logic;
begin begin
xCheck: TypeCheck xCheck: TypeCheck
port map (N => X, NaN => xNan, INF => xInf); port map (N => X, NAN => X_NAN, INF => X_INF);
yCheck: TypeCheck yCheck: TypeCheck
port map (N => Y, NaN => yNan, INF => yInf); port map (N => Y, NAN => Y_NAN, INF => Y_INF);
xSign <= X(31); X_SIGN <= X(31);
ySign <= Y(31); Y_SIGN <= Y(31);
isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign); IS_NAN <= X_NAN or Y_NAN or (X_INF and X_SIGN and Y_INF and (not Y_SIGN)) or (X_INF and (not X_SIGN) and Y_INF and Y_SIGN);
end NaNCheckArch; end NaNCheckArch;

21
SpecialCasesCheck.vhd
View File

@@ -2,32 +2,43 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity SpecialCasesCheck is entity SpecialCasesCheck is
port( port(
X, Y : in std_logic_vector(31 downto 0); X, Y : in std_logic_vector(31 downto 0);
isNaN, isZero: out std_logic IS_NAN, IS_ZERO : out std_logic
); );
end SpecialCasesCheck; end SpecialCasesCheck;
architecture SpecialCasesCheckArch of SpecialCasesCheck is architecture SpecialCasesCheckArch of SpecialCasesCheck is
component NaNCheck is component NaNCheck is
port( port(
X, Y : in std_logic_vector(31 downto 0); X, Y : in std_logic_vector(31 downto 0);
isNaN: out std_logic IS_NAN : out std_logic
); );
end component; end component;
component ZeroCheck is component ZeroCheck is
port( port(
X, Y : in std_logic_vector(31 downto 0); X, Y : in std_logic_vector(31 downto 0);
isZero: out std_logic IS_ZERO : out std_logic
); );
end component; end component;
begin begin
NC: NaNCheck NC: NaNCheck
port map (X => X, Y => Y, isNaN => isNaN); port map (X => X, Y => Y, IS_NAN => IS_NAN);
ZC: ZeroCheck ZC: ZeroCheck
port map (X => X, Y => Y, isZero => isZero); port map (X => X, Y => Y, IS_ZERO => IS_ZERO);
end SpecialCasesCheckArch; end SpecialCasesCheckArch;

17
Swap.vhd
View File

@@ -2,25 +2,32 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity Swap is entity Swap is
generic(BITCOUNT : integer := 8);
generic(
BITCOUNT : integer := 8
);
port( port(
X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0); X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
SW : in std_logic; SW : in std_logic;
X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0) X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
); );
end Swap; end Swap;
architecture SwapArch of Swap is architecture SwapArch of Swap is
begin begin
SWAP_PRO: process(X_IN, Y_IN, SW)
begin
for i in (BITCOUNT-1) downto 0 loop
SWAP_PROCESS: process(X_IN, Y_IN, SW)
begin
for i in (BITCOUNT-1) downto 0 loop
X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i)); X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i));
Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i)); Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i));
end loop; end loop;
end process; end process;
end SwapArch; end SwapArch;

45
TwoComplement.vhd
View File

@@ -2,30 +2,53 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity TwoComplement is entity TwoComplement is
generic(BITCOUNT : integer := 8);
generic(
BITCOUNT : integer := 8
);
port( port(
DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0); DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
DIFF_EXP_ABS : out std_logic_vector((BITCOUNT-2) downto 0); DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
); );
end TwoComplement; end TwoComplement;
architecture TwoComplementArch of TwoComplement is architecture TwoComplementArch of TwoComplement is
signal S : std_logic;
signal M : std_logic_vector((BITCOUNT-2) downto 0);
begin
S <= DIFF_EXP_C2(BITCOUNT-1);
M <= DIFF_EXP_C2((BITCOUNT-2) downto 0);
C2 : process(DIFF_EXP_C2) signal SIGN : std_logic;
signal DIFF_EXP_ABS : std_logic_vector((BITCOUNT-2) downto 0);
begin begin
SIGN <= DIFF_EXP_C2(BITCOUNT-1);
C2_PROCESS : process(DIFF_EXP_C2, SIGN)
begin
for i in (BITCOUNT-2) downto 0 loop for i in (BITCOUNT-2) downto 0 loop
M(i) <= S xor M(i); DIFF_EXP_ABS(i) <= SIGN xor DIFF_EXP_C2(i);
end loop; end loop;
end process; end process;
--sommare 1 a M se S = '1' SUM : process(DIFF_EXP_ABS, SIGN)
DIFF_EXP_ABS <= M; variable CARRY : std_logic;
begin
CARRY := SIGN;
for i in 0 to (BITCOUNT-2) loop
DIFF_EXP(i) <= DIFF_EXP_ABS(i) xor CARRY;
CARRY := DIFF_EXP_ABS(i) and CARRY;
end loop;
DIFF_EXP(BITCOUNT-1) <= CARRY;
end process;
end TwoComplementArch; end TwoComplementArch;

85
TwoComplementTest.vhd Normal file
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@@ -0,0 +1,85 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TwoComplementTest IS
END TwoComplementTest;
ARCHITECTURE behavior OF TwoComplementTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TwoComplement
PORT(
DIFF_EXP_C2 : IN std_logic_vector(7 downto 0);
DIFF_EXP : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000";
--Outputs
signal DIFF_EXP : std_logic_vector(7 downto 0);
signal clock : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TwoComplement PORT MAP (
DIFF_EXP_C2 => DIFF_EXP_C2,
DIFF_EXP => DIFF_EXP
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
test_process :process
begin
DIFF_EXP_C2 <= "01001110";
wait for clock_period;
DIFF_EXP_C2 <= "11111111";
wait for clock_period;
DIFF_EXP_C2 <= "10000000";
wait for clock_period;
DIFF_EXP_C2 <= "01111111";
wait for clock_period;
DIFF_EXP_C2 <= "01100101";
wait for clock_period;
DIFF_EXP_C2 <= "10011101";
wait for clock_period;
DIFF_EXP_C2 <= "11100010";
wait for clock_period;
DIFF_EXP_C2 <= "10010011";
wait for clock_period;
end process;
END;

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TwoComplementTest_isim_beh.wdb Normal file
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56
TypeCheck.vhd
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@@ -2,42 +2,60 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity TypeCheck is entity TypeCheck is
port( port(
N : in std_logic_vector(31 downto 0); N : in std_logic_vector(31 downto 0);
NaN, INF: out std_logic NAN, INF : out std_logic
); );
end TypeCheck; end TypeCheck;
architecture TypeCheckArch of TypeCheck is architecture TypeCheckArch of TypeCheck is
signal G_Bus: std_logic_vector(7 downto 0);
signal T_Bus: std_logic_vector(22 downto 0); signal G_BUS : std_logic_vector(7 downto 0);
signal T_BUS : std_logic_vector(22 downto 0);
signal G : std_logic := '1'; signal G : std_logic := '1';
signal T : std_logic := '0'; signal T : std_logic := '0';
begin
G_Bus <= N(30 downto 23);
T_Bus <= N(22 downto 0);
G_compute: process (G_Bus)
variable G_tmp: std_logic;
begin begin
G_tmp := '1';
for i in G_Bus'range loop G_BUS <= N(30 downto 23);
G_tmp := G_tmp and G_Bus(i); T_BUS <= N(22 downto 0);
G_compute: process (G_BUS)
variable G_TMP : std_logic;
begin
G_TMP := '1';
for i in G_BUS'range loop
G_TMP := G_TMP and G_BUS(i);
end loop; end loop;
G <= G_tmp;
G <= G_TMP;
end process; end process;
T_compute: process (T_Bus) T_compute: process (T_BUS)
variable T_tmp: std_logic;
variable T_TMP : std_logic;
begin begin
T_tmp := '0';
for i in T_Bus'range loop T_TMP := '0';
T_tmp := T_tmp or T_Bus(i);
for i in T_BUS'range loop
T_TMP := T_TMP or T_BUS(i);
end loop; end loop;
T <= T_tmp;
T <= T_TMP;
end process; end process;
NaN <= G and T; NAN <= G and T;
INF <= G and (not T); INF <= G and (not T);
end TypeCheckArch; end TypeCheckArch;

46
ZeroCheck.vhd
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@@ -3,38 +3,50 @@ use IEEE.STD_LOGIC_1164.ALL;
entity ZeroCheck is entity ZeroCheck is
port( port(
X, Y : in std_logic_vector(31 downto 0); X, Y : in std_logic_vector(31 downto 0);
isZero: out std_logic IS_ZERO : out std_logic
); );
end ZeroCheck; end ZeroCheck;
architecture ZeroCheckArch of ZeroCheck is architecture ZeroCheckArch of ZeroCheck is
component EqualCheck is component EqualCheck is
generic( BITCOUNT: integer := 8 );
generic(
BITCOUNT : integer := 8
);
port( port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0); X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
isEqual: out std_logic IS_EQUAL : out std_logic
); );
end component; end component;
signal xSign: std_logic; signal S_SIGN : std_logic;
signal ySign: std_logic; signal Y_SIGN : std_logic;
signal xAbs: std_logic_vector(30 downto 0); signal X_ABS : std_logic_vector(30 downto 0);
signal yAbs: std_logic_vector(30 downto 0); signal Y_ABS : std_logic_vector(30 downto 0);
signal isSameAbsValue: std_logic; signal IS_SAME_ABS_VALUE : std_logic;
signal isSameSign: std_logic; signal IS_SAME_SIGN : std_logic;
begin
xSign <= X(31); begin
ySign <= Y(31);
xAbs <= X(30 downto 0); S_SIGN <= X(31);
yAbs <= Y(30 downto 0); Y_SIGN <= Y(31);
X_ABS <= X(30 downto 0);
Y_ABS <= Y(30 downto 0);
IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
isSameSign <= xSign xnor ySign;
AbsCheck: EqualCheck AbsCheck: EqualCheck
generic map ( BITCOUNT => 31 ) generic map ( BITCOUNT => 31 )
port map (X => xAbs, Y => yAbs, isEqual => isSameAbsValue); port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);
IS_ZERO <= (not IS_SAME_SIGN) and IS_SAME_ABS_VALUE;
isZero <= (not isSameSign) and isSameAbsValue;
end ZeroCheckArch; end ZeroCheckArch;

36
equalCheck.vhd
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@@ -2,26 +2,40 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity EqualCheck is entity EqualCheck is
generic( BITCOUNT: integer := 8 );
generic(
BITCOUNT: integer := 8
);
port( port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0); X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
isEqual: out std_logic IS_EQUAL : out std_logic
); );
end EqualCheck; end EqualCheck;
architecture EqualCheckArch of EqualCheck is architecture EqualCheckArch of EqualCheck is
signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
begin
compVec <= X xor Y;
res_compute: process (compVec) signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
variable res_tmp: std_logic;
begin begin
res_tmp := '0';
for i in compVec'range loop COMP_VEC <= X xor Y;
res_tmp := res_tmp or compVec(i);
RES_COMPUTE: process (COMP_VEC)
variable RES_TMP : std_logic;
begin
RES_TMP := '0';
for i in COMP_VEC'range loop
RES_TMP := RES_TMP or COMP_VEC(i);
end loop; end loop;
isEqual <= not res_tmp;
IS_EQUAL <= not RES_TMP;
end process; end process;
end EqualCheckArch; end EqualCheckArch;

20
fuse.log
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@@ -1,21 +1,21 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest" Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest
ISim P.20160913 (signature 0xfbc00daa) ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1 Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0 Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work
Starting static elaboration Starting static elaboration
Completed static elaboration Completed static elaboration
Fuse Memory Usage: 95308 KB Fuse Memory Usage: 95308 KB
Fuse CPU Usage: 2530 ms Fuse CPU Usage: 2300 ms
Compiling package standard Compiling package standard
Compiling package std_logic_1164 Compiling package std_logic_1164
Compiling architecture fulladderarch of entity FullAdder [fulladder_default] Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
Compiling architecture behavior of entity fulladdertest Compiling architecture behavior of entity twocomplementtest
Time Resolution for simulation is 1ps. Time Resolution for simulation is 1ps.
Compiled 5 VHDL Units Compiled 5 VHDL Units
Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
Fuse Memory Usage: 103940 KB Fuse Memory Usage: 103960 KB
Fuse CPU Usage: 2640 ms Fuse CPU Usage: 2400 ms
GCC CPU Usage: 440 ms GCC CPU Usage: 1480 ms

2
fuseRelaunch.cmd
View File

@@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest" -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest"

12
isim.log
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@@ -1,5 +1,5 @@
ISim log file ISim log file
Running: /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.wdb Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb
ISim P.20160913 (signature 0xfbc00daa) ISim P.20160913 (signature 0xfbc00daa)
---------------------------------------------------------------------- ----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
@@ -13,14 +13,4 @@ Time resolution is 1 ps
# run 1000 ns # run 1000 ns
Simulator is doing circuit initialization process. Simulator is doing circuit initialization process.
Finished circuit initialization process. Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0 # exit 0

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isim/ComparatorTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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28
isim/ComparatorTest_isim_beh.exe.sim/isimkernel.log
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@@ -1,28 +0,0 @@
Command line:
ComparatorTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 40809
Tue Aug 27 09:47:36 2019
Elaboration Time: 0.12 sec
Current Memory Usage: 198.607 Meg
Total Signals : 9
Total Nets : 34
Total Signal Drivers : 4
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 5
Total Traceable Variables : 10
Total Scalar Nets and Variables : 396
Total Simulation Time: 0.13 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 09:47:41 2019

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isim/ComparatorTest_isim_beh.exe.sim/netId.dat
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isim/ComparatorTest_isim_beh.exe.sim/tmp_save/_1
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40
isim/ComparatorTest_isim_beh.exe.sim/work/ComparatorTest_isim_beh.exe_main.c
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@@ -1,40 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0883098610_0495709306_init();
work_a_1038528572_2372691052_init();
xsi_register_tops("work_a_1038528572_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

314
isim/ComparatorTest_isim_beh.exe.sim/work/a_0883098610_0495709306.c
View File

@@ -1,314 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/Comparator.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0883098610_0495709306_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 6144U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 6160U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4112);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4000);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 6144U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 6160U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4176);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4016);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
char *t9;
int t10;
int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
int t21;
unsigned int t22;
unsigned int t23;
unsigned int t24;
char *t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
LAB0: xsi_set_current_line(24, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(25, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(26, ng0);
t3 = (8 - 1);
t1 = (t0 + 6254);
*((int *)t1) = t3;
t2 = (t0 + 6258);
*((int *)t2) = 0;
t4 = t3;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: xsi_set_current_line(30, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 4240);
t6 = (t1 + 56U);
t7 = *((char **)t6);
t9 = (t7 + 56U);
t15 = *((char **)t9);
*((unsigned char *)t15) = t8;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4032);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(27, ng0);
t6 = (t0 + 2088U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t6 = (t0 + 1512U);
t9 = *((char **)t6);
t6 = (t0 + 6254);
t10 = *((int *)t6);
t11 = (t10 - 7);
t12 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t13 = (1U * t12);
t14 = (0 + t13);
t15 = (t9 + t14);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = (t0 + 1672U);
t19 = *((char **)t18);
t18 = (t0 + 6254);
t20 = *((int *)t18);
t21 = (t20 - 7);
t22 = (t21 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t18));
t23 = (1U * t22);
t24 = (0 + t23);
t25 = (t19 + t24);
t26 = *((unsigned char *)t25);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t17, t26);
t28 = (t0 + 2208U);
t29 = *((char **)t28);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t27, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t8, t31);
t28 = (t0 + 2088U);
t33 = *((char **)t28);
t28 = (t33 + 0);
*((unsigned char *)t28) = t32;
xsi_set_current_line(28, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 1512U);
t6 = *((char **)t1);
t1 = (t0 + 6254);
t3 = *((int *)t1);
t10 = (t3 - 7);
t12 = (t10 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t1));
t13 = (1U * t12);
t14 = (0 + t13);
t7 = (t6 + t14);
t16 = *((unsigned char *)t7);
t9 = (t0 + 1672U);
t15 = *((char **)t9);
t9 = (t0 + 6254);
t11 = *((int *)t9);
t20 = (t11 - 7);
t22 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t9));
t23 = (1U * t22);
t24 = (0 + t23);
t18 = (t15 + t24);
t17 = *((unsigned char *)t18);
t26 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t17);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t26);
t30 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t27);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t30);
t19 = (t0 + 2208U);
t25 = *((char **)t19);
t19 = (t25 + 0);
*((unsigned char *)t19) = t31;
LAB4: t1 = (t0 + 6254);
t4 = *((int *)t1);
t2 = (t0 + 6258);
t5 = *((int *)t2);
if (t4 == t5)
goto LAB5;
LAB6: t3 = (t4 + -1);
t4 = t3;
t6 = (t0 + 6254);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_0883098610_0495709306_init()
{
static char *pe[] = {(void *)work_a_0883098610_0495709306_p_0,(void *)work_a_0883098610_0495709306_p_1,(void *)work_a_0883098610_0495709306_p_2};
xsi_register_didat("work_a_0883098610_0495709306", "isim/ComparatorTest_isim_beh.exe.sim/work/a_0883098610_0495709306.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/ComparatorTest.vhd";
static void work_a_1038528572_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2784U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(45, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(46, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(47, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(48, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_1038528572_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3032U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(56, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2840);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(58, ng0);
t2 = (t0 + 1808U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2840);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(62, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_1038528572_2372691052_init()
{
static char *pe[] = {(void *)work_a_1038528572_2372691052_p_0,(void *)work_a_1038528572_2372691052_p_1};
xsi_register_didat("work_a_1038528572_2372691052", "isim/ComparatorTest_isim_beh.exe.sim/work/a_1038528572_2372691052.didat");
xsi_register_executes(pe);
}

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Command line:
FullAdderTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 51967
Tue Aug 27 15:05:31 2019
Elaboration Time: 0.11 sec
Current Memory Usage: 198.607 Meg
Total Signals : 11
Total Nets : 6
Total Signal Drivers : 6
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 4
Total Traceable Variables : 9
Total Scalar Nets and Variables : 367
Total Simulation Time: 0.15 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 15:08:11 2019

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isim/FullAdderTest_isim_beh.exe.sim/work/FullAdderTest_isim_beh.exe_main.c
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_1130988942_2801528920_init();
work_a_2258021406_2372691052_init();
xsi_register_tops("work_a_2258021406_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/FullAdder.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768497506413324_503743352(char *, unsigned char , unsigned char );
static void work_a_1130988942_2801528920_p_0(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t13;
char *t14;
LAB0: xsi_set_current_line(14, ng0);
LAB3: t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1032U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1192U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t9 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t6, t8);
t1 = (t0 + 3488);
t10 = (t1 + 56U);
t11 = *((char **)t10);
t12 = (t11 + 56U);
t13 = *((char **)t12);
*((unsigned char *)t13) = t9;
xsi_driver_first_trans_fast_port(t1);
LAB2: t14 = (t0 + 3392);
*((int *)t14) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1130988942_2801528920_p_1(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
unsigned char t12;
char *t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
LAB0: xsi_set_current_line(15, ng0);
LAB3: t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1032U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1352U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1192U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t12 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t11);
t1 = (t0 + 1032U);
t13 = *((char **)t1);
t14 = *((unsigned char *)t13);
t1 = (t0 + 1192U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t16);
t18 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t12, t17);
t1 = (t0 + 3552);
t19 = (t1 + 56U);
t20 = *((char **)t19);
t21 = (t20 + 56U);
t22 = *((char **)t21);
*((unsigned char *)t22) = t18;
xsi_driver_first_trans_fast_port(t1);
LAB2: t23 = (t0 + 3408);
*((int *)t23) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1130988942_2801528920_init()
{
static char *pe[] = {(void *)work_a_1130988942_2801528920_p_0,(void *)work_a_1130988942_2801528920_p_1};
xsi_register_didat("work_a_1130988942_2801528920", "isim/FullAdderTest_isim_beh.exe.sim/work/a_1130988942_2801528920.didat");
xsi_register_executes(pe);
}

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isim/FullAdderTest_isim_beh.exe.sim/work/a_2258021406_2372691052.c
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@@ -1,427 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd";
static void work_a_2258021406_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(54, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(55, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(56, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(57, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_2258021406_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(63, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(64, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(65, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(66, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(67, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(68, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(69, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(70, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(71, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(72, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(73, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(74, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(75, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(76, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(77, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(78, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: xsi_set_current_line(79, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(80, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(81, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(82, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB22: *((char **)t1) = &&LAB23;
goto LAB1;
LAB17: goto LAB16;
LAB19: goto LAB17;
LAB20: xsi_set_current_line(83, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(84, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(85, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(86, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB26: *((char **)t1) = &&LAB27;
goto LAB1;
LAB21: goto LAB20;
LAB23: goto LAB21;
LAB24: xsi_set_current_line(87, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(88, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(89, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(90, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB30: *((char **)t1) = &&LAB31;
goto LAB1;
LAB25: goto LAB24;
LAB27: goto LAB25;
LAB28: xsi_set_current_line(91, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(92, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(93, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(94, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB34: *((char **)t1) = &&LAB35;
goto LAB1;
LAB29: goto LAB28;
LAB31: goto LAB29;
LAB32: goto LAB2;
LAB33: goto LAB32;
LAB35: goto LAB33;
}
extern void work_a_2258021406_2372691052_init()
{
static char *pe[] = {(void *)work_a_2258021406_2372691052_p_0,(void *)work_a_2258021406_2372691052_p_1};
xsi_register_didat("work_a_2258021406_2372691052", "isim/FullAdderTest_isim_beh.exe.sim/work/a_2258021406_2372691052.didat");
xsi_register_executes(pe);
}

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isim/NaNCheck_isim_beh.exe.sim/isimcrash.log
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isim/NaNCheck_isim_beh.exe.sim/isimkernel.log
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Command line:
NaNCheck_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 39524
Sat Aug 24 12:14:44 2019
Elaboration Time: 0.02 sec
Current Memory Usage: 195.346 Meg
Total Signals : 23
Total Nets : 137
Total Signal Drivers : 15
Total Blocks : 4
Total Primitive Blocks : 3
Total Processes : 15
Total Traceable Variables : 8
Total Scalar Nets and Variables : 497
Total Line Count : 27
Total Simulation Time: 0.04 sec
Current Memory Usage: 272.945 Meg
Sat Aug 24 12:14:54 2019

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isim/NaNCheck_isim_beh.exe.sim/work/NaNCheck_isim_beh.exe_main.c
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0557987184_1272247069_init();
work_a_4078426953_2628201599_init();
xsi_register_tops("work_a_4078426953_2628201599");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.c
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0557987184_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7603);
*((int *)t1) = 7;
t2 = (t0 + 7607);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7603);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7603);
t3 = *((int *)t1);
t2 = (t0 + 7607);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7603);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7611);
*((int *)t1) = 22;
t2 = (t0 + 7615);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7611);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7611);
t3 = *((int *)t1);
t2 = (t0 + 7615);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7611);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0557987184_1272247069_init()
{
static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5};
xsi_register_didat("work_a_0557987184_1272247069", "isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat");
xsi_register_executes(pe);
}

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isim/NaNCheck_isim_beh.exe.sim/work/a_4078426953_2628201599.c
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@@ -1,221 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_4078426953_2628201599_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(32, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4392);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4280);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4078426953_2628201599_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4456);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4296);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4078426953_2628201599_p_2(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
char *t12;
unsigned char t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
unsigned char t19;
char *t20;
unsigned char t21;
char *t22;
unsigned char t23;
unsigned char t24;
unsigned char t25;
char *t26;
unsigned char t27;
unsigned char t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
LAB0: xsi_set_current_line(35, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1672U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1832U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t1 = (t0 + 2152U);
t12 = *((char **)t1);
t13 = *((unsigned char *)t12);
t14 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t11, t13);
t1 = (t0 + 2312U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t17);
t19 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t18);
t1 = (t0 + 1672U);
t20 = *((char **)t1);
t21 = *((unsigned char *)t20);
t1 = (t0 + 1832U);
t22 = *((char **)t1);
t23 = *((unsigned char *)t22);
t24 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t23);
t25 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t24);
t1 = (t0 + 2152U);
t26 = *((char **)t1);
t27 = *((unsigned char *)t26);
t28 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t25, t27);
t1 = (t0 + 2312U);
t29 = *((char **)t1);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t28, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t19, t31);
t1 = (t0 + 4520);
t33 = (t1 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
*((unsigned char *)t36) = t32;
xsi_driver_first_trans_fast_port(t1);
LAB2: t37 = (t0 + 4312);
*((int *)t37) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_4078426953_2628201599_init()
{
static char *pe[] = {(void *)work_a_4078426953_2628201599_p_0,(void *)work_a_4078426953_2628201599_p_1,(void *)work_a_4078426953_2628201599_p_2};
xsi_register_didat("work_a_4078426953_2628201599", "isim/NaNCheck_isim_beh.exe.sim/work/a_4078426953_2628201599.didat");
xsi_register_executes(pe);
}

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isim/SpecialCasesTest_isim_beh.exe.sim/isimcrash.log
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Command line:
SpecialCasesTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 47173
Sat Aug 24 12:20:10 2019
Elaboration Time: 0.01 sec
Current Memory Usage: 195.359 Meg
Total Signals : 48
Total Nets : 239
Total Signal Drivers : 29
Total Blocks : 8
Total Primitive Blocks : 4
Total Processes : 26
Total Traceable Variables : 10
Total Scalar Nets and Variables : 601
Total Line Count : 143
Total Simulation Time: 0.04 sec
Current Memory Usage: 272.957 Meg
Sat Aug 24 14:38:35 2019

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isim/SpecialCasesTest_isim_beh.exe.sim/work/SpecialCasesTest_isim_beh.exe_main.c
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0557987184_1272247069_init();
work_a_3914402253_2628201599_init();
work_a_2347761600_1146481140_init();
work_a_1540508602_4151211736_init();
work_a_2912948712_3395701438_init();
work_a_4189535622_2372691052_init();
xsi_register_tops("work_a_4189535622_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0557987184_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7603);
*((int *)t1) = 7;
t2 = (t0 + 7607);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7603);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7603);
t3 = *((int *)t1);
t2 = (t0 + 7607);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7603);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7611);
*((int *)t1) = 22;
t2 = (t0 + 7615);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7611);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7611);
t3 = *((int *)t1);
t2 = (t0 + 7615);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7611);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0557987184_1272247069_init()
{
static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5};
xsi_register_didat("work_a_0557987184_1272247069", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_0557987184_1272247069.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3496108612141461530_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_1540508602_4151211736_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(28, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 5184);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 5024);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(29, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 5248);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 5040);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_2(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(30, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5312);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 31U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 5056);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_3(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(31, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5376);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 31U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 5072);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1672U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3496108612141461530_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5440);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast(t1);
LAB2: t11 = (t0 + 5088);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
unsigned char t4;
char *t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(38, ng0);
LAB3: t1 = (t0 + 2312U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t4 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t3);
t1 = (t0 + 2152U);
t5 = *((char **)t1);
t6 = *((unsigned char *)t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t4, t6);
t1 = (t0 + 5504);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5104);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1540508602_4151211736_init()
{
static char *pe[] = {(void *)work_a_1540508602_4151211736_p_0,(void *)work_a_1540508602_4151211736_p_1,(void *)work_a_1540508602_4151211736_p_2,(void *)work_a_1540508602_4151211736_p_3,(void *)work_a_1540508602_4151211736_p_4,(void *)work_a_1540508602_4151211736_p_5};
xsi_register_didat("work_a_1540508602_4151211736", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_1540508602_4151211736.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989833707593767_503743352(char *, char *, char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2347761600_1146481140_p_0(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(15, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 5352U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 5368U);
t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (31U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 3568);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 31U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 3472);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(31U, t9, 0);
goto LAB6;
}
static void work_a_2347761600_1146481140_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(20, ng0);
t1 = (t0 + 1928U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(21, ng0);
t1 = (t0 + 5506);
*((int *)t1) = 30;
t2 = (t0 + 5510);
*((int *)t2) = 0;
t3 = 30;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(24, ng0);
t1 = (t0 + 1928U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t15 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t7);
t1 = (t0 + 3632);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t15;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 3488);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(22, ng0);
t5 = (t0 + 1928U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 5506);
t9 = *((int *)t5);
t10 = (t9 - 30);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 1928U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 5506);
t3 = *((int *)t1);
t2 = (t0 + 5510);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 5506);
*((int *)t5) = t3;
goto LAB2;
}
extern void work_a_2347761600_1146481140_init()
{
static char *pe[] = {(void *)work_a_2347761600_1146481140_p_0,(void *)work_a_2347761600_1146481140_p_1};
xsi_register_didat("work_a_2347761600_1146481140", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_2347761600_1146481140.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
extern void work_a_2912948712_3395701438_init()
{
xsi_register_didat("work_a_2912948712_3395701438", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_2912948712_3395701438.didat");
}

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isim/SpecialCasesTest_isim_beh.exe.sim/work/a_3914402253_2628201599.c
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@@ -1,221 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_3914402253_2628201599_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(32, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4392);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4280);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3914402253_2628201599_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4456);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4296);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3914402253_2628201599_p_2(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
char *t12;
unsigned char t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
unsigned char t19;
char *t20;
unsigned char t21;
char *t22;
unsigned char t23;
unsigned char t24;
unsigned char t25;
char *t26;
unsigned char t27;
unsigned char t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
LAB0: xsi_set_current_line(35, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1672U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1832U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t1 = (t0 + 2152U);
t12 = *((char **)t1);
t13 = *((unsigned char *)t12);
t14 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t11, t13);
t1 = (t0 + 2312U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t17);
t19 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t18);
t1 = (t0 + 1672U);
t20 = *((char **)t1);
t21 = *((unsigned char *)t20);
t1 = (t0 + 1832U);
t22 = *((char **)t1);
t23 = *((unsigned char *)t22);
t24 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t23);
t25 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t24);
t1 = (t0 + 2152U);
t26 = *((char **)t1);
t27 = *((unsigned char *)t26);
t28 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t25, t27);
t1 = (t0 + 2312U);
t29 = *((char **)t1);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t28, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t19, t31);
t1 = (t0 + 4520);
t33 = (t1 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
*((unsigned char *)t36) = t32;
xsi_driver_first_trans_fast_port(t1);
LAB2: t37 = (t0 + 4312);
*((int *)t37) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_3914402253_2628201599_init()
{
static char *pe[] = {(void *)work_a_3914402253_2628201599_p_0,(void *)work_a_3914402253_2628201599_p_1,(void *)work_a_3914402253_2628201599_p_2};
xsi_register_didat("work_a_3914402253_2628201599", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_3914402253_2628201599.didat");
xsi_register_executes(pe);
}

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Command line:
SwapTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 45337
Tue Aug 27 12:56:25 2019
Elaboration Time: 0.09 sec
Current Memory Usage: 198.603 Meg
Total Signals : 11
Total Nets : 34
Total Signal Drivers : 3
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 3
Total Traceable Variables : 10
Total Scalar Nets and Variables : 396
Total Simulation Time: 0.11 sec
Current Memory Usage: 276.201 Meg
Tue Aug 27 12:56:46 2019

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/SwapTest.vhd";
static void work_a_0464846403_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(54, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(55, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(56, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(57, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_0464846403_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(65, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(67, ng0);
t2 = (t0 + 2128U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 3160);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(71, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_0464846403_2372691052_init()
{
static char *pe[] = {(void *)work_a_0464846403_2372691052_p_0,(void *)work_a_0464846403_2372691052_p_1};
xsi_register_didat("work_a_0464846403_2372691052", "isim/SwapTest_isim_beh.exe.sim/work/a_0464846403_2372691052.didat");
xsi_register_executes(pe);
}

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isim/SwapTest_isim_beh.exe.sim/work/a_0464846403_2372691052.didat
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isim/SwapTest_isim_beh.exe.sim/work/a_0464846403_2372691052.lin64.o
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207
isim/SwapTest_isim_beh.exe.sim/work/a_2579272516_1004118533.c
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@@ -1,207 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/Swap.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2579272516_1004118533_p_0(char *t0)
{
int t1;
char *t2;
char *t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
unsigned char t9;
char *t10;
int t11;
int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
char *t16;
unsigned char t17;
unsigned char t18;
char *t19;
char *t20;
unsigned char t21;
char *t22;
int t23;
int t24;
unsigned int t25;
unsigned int t26;
unsigned int t27;
char *t28;
unsigned char t29;
unsigned char t30;
unsigned char t31;
char *t32;
int t33;
int t34;
unsigned int t35;
unsigned int t36;
unsigned int t37;
char *t38;
char *t39;
char *t40;
char *t41;
char *t42;
LAB0: xsi_set_current_line(18, ng0);
t1 = (8 - 1);
t2 = (t0 + 5109);
*((int *)t2) = t1;
t3 = (t0 + 5113);
*((int *)t3) = 0;
t4 = t1;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: t2 = (t0 + 3264);
*((int *)t2) = 1;
LAB1: return;
LAB3: xsi_set_current_line(20, ng0);
t6 = (t0 + 1352U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t9 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t8);
t6 = (t0 + 1032U);
t10 = *((char **)t6);
t6 = (t0 + 5109);
t11 = *((int *)t6);
t12 = (t11 - 7);
t13 = (t12 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t14 = (1U * t13);
t15 = (0 + t14);
t16 = (t10 + t15);
t17 = *((unsigned char *)t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t9, t17);
t19 = (t0 + 1352U);
t20 = *((char **)t19);
t21 = *((unsigned char *)t20);
t19 = (t0 + 1192U);
t22 = *((char **)t19);
t19 = (t0 + 5109);
t23 = *((int *)t19);
t24 = (t23 - 7);
t25 = (t24 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t19));
t26 = (1U * t25);
t27 = (0 + t26);
t28 = (t22 + t27);
t29 = *((unsigned char *)t28);
t30 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t29);
t31 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t18, t30);
t32 = (t0 + 5109);
t33 = *((int *)t32);
t34 = (t33 - 7);
t35 = (t34 * -1);
t36 = (1 * t35);
t37 = (0U + t36);
t38 = (t0 + 3344);
t39 = (t38 + 56U);
t40 = *((char **)t39);
t41 = (t40 + 56U);
t42 = *((char **)t41);
*((unsigned char *)t42) = t31;
xsi_driver_first_trans_delta(t38, t37, 1, 0LL);
xsi_set_current_line(21, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t8 = *((unsigned char *)t3);
t9 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t8);
t2 = (t0 + 1192U);
t6 = *((char **)t2);
t2 = (t0 + 5109);
t1 = *((int *)t2);
t11 = (t1 - 7);
t13 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t2));
t14 = (1U * t13);
t15 = (0 + t14);
t7 = (t6 + t15);
t17 = *((unsigned char *)t7);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t9, t17);
t10 = (t0 + 1352U);
t16 = *((char **)t10);
t21 = *((unsigned char *)t16);
t10 = (t0 + 1032U);
t19 = *((char **)t10);
t10 = (t0 + 5109);
t12 = *((int *)t10);
t23 = (t12 - 7);
t25 = (t23 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t10));
t26 = (1U * t25);
t27 = (0 + t26);
t20 = (t19 + t27);
t29 = *((unsigned char *)t20);
t30 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t29);
t31 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t18, t30);
t22 = (t0 + 5109);
t24 = *((int *)t22);
t33 = (t24 - 7);
t35 = (t33 * -1);
t36 = (1 * t35);
t37 = (0U + t36);
t28 = (t0 + 3408);
t32 = (t28 + 56U);
t38 = *((char **)t32);
t39 = (t38 + 56U);
t40 = *((char **)t39);
*((unsigned char *)t40) = t31;
xsi_driver_first_trans_delta(t28, t37, 1, 0LL);
LAB4: t2 = (t0 + 5109);
t4 = *((int *)t2);
t3 = (t0 + 5113);
t5 = *((int *)t3);
if (t4 == t5)
goto LAB5;
LAB6: t1 = (t4 + -1);
t4 = t1;
t6 = (t0 + 5109);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_2579272516_1004118533_init()
{
static char *pe[] = {(void *)work_a_2579272516_1004118533_p_0};
xsi_register_didat("work_a_2579272516_1004118533", "isim/SwapTest_isim_beh.exe.sim/work/a_2579272516_1004118533.didat");
xsi_register_executes(pe);
}

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isim/SwapTest_isim_beh.exe.sim/work/a_2579272516_1004118533.lin64.o
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isim/TwoComplementTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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isim/SwapTest_isim_beh.exe.sim/SwapTest_isim_beh.exe → isim/TwoComplementTest_isim_beh.exe.sim/TwoComplementTest_isim_beh.exe
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0
isim/ComparatorTest_isim_beh.exe.sim/isimcrash.log → isim/TwoComplementTest_isim_beh.exe.sim/isimcrash.log
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28
isim/TwoComplementTest_isim_beh.exe.sim/isimkernel.log Normal file
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@@ -0,0 +1,28 @@
Command line:
TwoComplementTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 59889
Thu Aug 29 13:06:30 2019
Elaboration Time: 0.13 sec
Current Memory Usage: 198.607 Meg
Total Signals : 7
Total Nets : 25
Total Signal Drivers : 5
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 6
Total Traceable Variables : 10
Total Scalar Nets and Variables : 387
Total Simulation Time: 0.17 sec
Current Memory Usage: 276.206 Meg
Thu Aug 29 13:10:59 2019

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isim/TwoComplementTest_isim_beh.exe.sim/netId.dat Normal file
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isim/TwoComplementTest_isim_beh.exe.sim/tmp_save/_1 Normal file
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6
isim/SwapTest_isim_beh.exe.sim/work/SwapTest_isim_beh.exe_main.c → isim/TwoComplementTest_isim_beh.exe.sim/work/TwoComplementTest_isim_beh.exe_main.c
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@@ -25,11 +25,11 @@ int main(int argc, char **argv)
xsi_register_min_prec_unit(-12); xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init(); ieee_p_2592010699_init();
work_a_2579272516_1004118533_init(); work_a_3935631676_2318913362_init();
work_a_0464846403_2372691052_init(); work_a_2858062612_2372691052_init();
xsi_register_tops("work_a_0464846403_2372691052"); xsi_register_tops("work_a_2858062612_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699"); IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699); xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

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