Aggiunti test
This commit is contained in:
@@ -13,9 +13,9 @@ ARCHITECTURE behavior OF AddSubTest IS
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PORT(
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X : IN std_logic_vector(7 downto 0);
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Y : IN std_logic_vector(7 downto 0);
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isSub : IN std_logic;
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result : OUT std_logic_vector(7 downto 0);
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overflow : OUT std_logic
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IS_SUB : IN std_logic;
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RESULT : OUT std_logic_vector(7 downto 0);
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OVERFLOW : OUT std_logic
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);
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END COMPONENT;
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@@ -23,11 +23,11 @@ ARCHITECTURE behavior OF AddSubTest IS
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--Inputs
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signal X : std_logic_vector(7 downto 0) := (others => '0');
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signal Y : std_logic_vector(7 downto 0) := (others => '0');
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signal isSub : std_logic := '0';
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signal IS_SUB : std_logic := '0';
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--Outputs
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signal result : std_logic_vector(7 downto 0);
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signal overflow : std_logic;
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signal RESULT : std_logic_vector(7 downto 0);
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signal OVERFLOW : std_logic;
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signal clock: std_logic;
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constant clock_period : time := 10 ns;
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@@ -38,9 +38,9 @@ BEGIN
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uut: AddSub PORT MAP (
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X => X,
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Y => Y,
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isSub => isSub,
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result => result,
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overflow => overflow
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IS_SUB => IS_SUB,
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RESULT => RESULT,
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OVERFLOW => OVERFLOW
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);
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-- Clock process definitions
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@@ -57,70 +57,70 @@ BEGIN
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begin
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X <= "00110011";
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Y <= "11001100";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "10010111";
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Y <= "11100011";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "10000101";
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Y <= "01111011";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "11111111";
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Y <= "11111111";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "00101011";
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Y <= "00101010";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "11111111";
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Y <= "11111111";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "10000000";
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Y <= "10000000";
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isSub <= '0';
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IS_SUB <= '0';
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wait for clock_period;
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X <= "00000000";
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Y <= "11111111";
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isSub <= '0';
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IS_SUB <= '0';
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X <= "00110011";
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Y <= "11001100";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "10010111";
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Y <= "11100011";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "10000101";
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Y <= "01111011";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "11111111";
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Y <= "11111111";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "00101011";
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Y <= "00101010";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "11111111";
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Y <= "11111111";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "10000000";
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Y <= "10000000";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "00000000";
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Y <= "11111111";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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X <= "11111111";
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Y <= "00000000";
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isSub <= '1';
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IS_SUB <= '1';
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wait for clock_period;
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end process;
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Binary file not shown.
Binary file not shown.
@@ -8,27 +8,25 @@ ARCHITECTURE behavior OF AdderTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Adder
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COMPONENT CarryLookAhead
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PORT(
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X : IN std_logic_vector(7 downto 0);
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Y : IN std_logic_vector(7 downto 0);
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carry_in : IN std_logic;
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result : OUT std_logic_vector(7 downto 0);
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carry_out : OUT std_logic
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X : IN std_logic_vector(47 downto 0);
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Y : IN std_logic_vector(47 downto 0);
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OP : IN std_logic;
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RESULT : OUT std_logic_vector(47 downto 0);
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OVERFLOW : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(7 downto 0) := (others => '0');
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signal Y : std_logic_vector(7 downto 0) := (others => '0');
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signal carry_in : std_logic := '0';
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signal X : std_logic_vector(47 downto 0) := (others => '0');
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signal Y : std_logic_vector(47 downto 0) := (others => '0');
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signal OP : std_logic := '0';
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--Outputs
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signal result : std_logic_vector(7 downto 0);
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signal carry_out : std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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signal RESULT : std_logic_vector(47 downto 0);
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signal OVERFLOW : std_logic;
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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@@ -36,12 +34,12 @@ ARCHITECTURE behavior OF AdderTest IS
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Adder PORT MAP (
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uut: CarryLookAhead PORT MAP (
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X => X,
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Y => Y,
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carry_in => carry_in,
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result => result,
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carry_out => carry_out
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OP => OP,
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RESULT => RESULT,
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OVERFLOW => OVERFLOW
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);
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-- Clock process definitions
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@@ -53,7 +51,10 @@ BEGIN
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wait for clock_period/2;
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end process;
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x <= "00010101";
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y <= "00001110";
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test_proc: process
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begin
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--test
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wait for clock_period;
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end process;
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END;
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@@ -11,21 +11,19 @@ ARCHITECTURE behavior OF ComparatorTest IS
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COMPONENT Comparator
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PORT(
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xT : IN std_logic_vector(7 downto 0);
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yT : IN std_logic_vector(7 downto 0);
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needSwap : OUT std_logic
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X_MANT : IN std_logic_vector(7 downto 0);
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Y_MANT : IN std_logic_vector(7 downto 0);
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NEED_SWAP : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal xT : std_logic_vector(7 downto 0) := "11111111";
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signal yT : std_logic_vector(7 downto 0) := "11111111";
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signal X_MANT : std_logic_vector(7 downto 0) := (others => '0');
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signal Y_MANT : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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signal needSwap : std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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signal NEED_SWAP : std_logic;
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signal clock: std_logic;
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constant clock_period : time := 10 ns;
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@@ -34,9 +32,9 @@ BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Comparator PORT MAP (
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xT => xT,
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yT => yT,
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needSwap => needSwap
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X_MANT => X_MANT,
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Y_MANT => Y_MANT,
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NEED_SWAP => NEED_SWAP
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);
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-- Clock process definitions
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@@ -48,18 +46,32 @@ BEGIN
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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test_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clock_period*10;
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-- insert stimulus here
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wait;
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X_MANT <= "00000000";
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Y_MANT <= "00000000";
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wait for clock_period;
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X_MANT <= "01011010";
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Y_MANT <= "01100000";
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wait for clock_period;
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X_MANT <= "00111100";
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Y_MANT <= "10000100";
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wait for clock_period;
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X_MANT <= "10000000";
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Y_MANT <= "01111111";
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wait for clock_period;
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X_MANT <= "01110100";
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Y_MANT <= "01101000";
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wait for clock_period;
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X_MANT <= "01111111";
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Y_MANT <= "10000000";
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wait for clock_period;
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X_MANT <= "10101010";
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Y_MANT <= "01010101";
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wait for clock_period;
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X_MANT <= "01010101";
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Y_MANT <= "10101010";
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wait for clock_period;
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end process;
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END;
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@@ -43,7 +43,7 @@
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</file>
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<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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@@ -53,7 +53,7 @@
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</file>
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<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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@@ -66,7 +66,7 @@
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
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</file>
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<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
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@@ -74,41 +74,71 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
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</file>
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<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="179"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="179"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="179"/>
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</file>
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<file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="244"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="255"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
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||||
<file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="256"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
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||||
<file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="266"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="266"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="266"/>
|
||||
</file>
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||||
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="274"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="274"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="274"/>
|
||||
</file>
|
||||
<file xil_pn:name="OperationCheckTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="276"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="276"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="276"/>
|
||||
</file>
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||||
<file xil_pn:name="PrepareForShiftTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="277"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="277"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="277"/>
|
||||
</file>
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<file xil_pn:name="ShiftRight48Test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="279"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="279"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
|
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</file>
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</files>
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<properties>
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@@ -229,9 +259,9 @@
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<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PrepareForShift|PrepareForShiftArch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="PrepareForShift.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PrepareForShift" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SumDataAdapter|SumDataAdapterArch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="SumDataAdapter.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SumDataAdapter" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -300,7 +330,7 @@
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="PrepareForShift" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="SumDataAdapter" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@@ -315,10 +345,10 @@
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PrepareForShift_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="PrepareForShift_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PrepareForShift_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PrepareForShift_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SumDataAdapter_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="SumDataAdapter_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SumDataAdapter_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SumDataAdapter_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -367,8 +397,8 @@
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ShiftRight" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ShiftRight" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SumDataAdapterTest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@@ -387,7 +417,7 @@
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ShiftRight" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
@@ -443,7 +473,7 @@
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SumDataAdapterTest|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
||||
68
OperationCheckTest.vhd
Normal file
68
OperationCheckTest.vhd
Normal file
@@ -0,0 +1,68 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY OperationCheckTest IS
|
||||
END OperationCheckTest;
|
||||
|
||||
ARCHITECTURE behavior OF OperationCheckTest IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT OperationCheck
|
||||
PORT(
|
||||
X_SIGN : IN std_logic;
|
||||
Y_SIGN : IN std_logic;
|
||||
OP : OUT std_logic;
|
||||
RES_SIGN : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal X_SIGN : std_logic := '0';
|
||||
signal Y_SIGN : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal OP : std_logic;
|
||||
signal RES_SIGN : std_logic;
|
||||
signal clock : std_logic;
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: OperationCheck PORT MAP (
|
||||
X_SIGN => X_SIGN,
|
||||
Y_SIGN => Y_SIGN,
|
||||
OP => OP,
|
||||
RES_SIGN => RES_SIGN
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clock_process :process
|
||||
begin
|
||||
clock <= '0';
|
||||
wait for clock_period/2;
|
||||
clock <= '1';
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
test_proc: process
|
||||
begin
|
||||
X_SIGN <= '0';
|
||||
Y_SIGN <= '0';
|
||||
wait for clock_period;
|
||||
X_SIGN <= '0';
|
||||
Y_SIGN <= '1';
|
||||
wait for clock_period;
|
||||
X_SIGN <= '1';
|
||||
Y_SIGN <= '0';
|
||||
wait for clock_period;
|
||||
X_SIGN <= '1';
|
||||
Y_SIGN <= '1';
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
END;
|
||||
BIN
OperationCheckTest_isim_beh.exe
Normal file
BIN
OperationCheckTest_isim_beh.exe
Normal file
Binary file not shown.
84
PrepareForShiftTest.vhd
Normal file
84
PrepareForShiftTest.vhd
Normal file
@@ -0,0 +1,84 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY PrepareForShiftTest IS
|
||||
END PrepareForShiftTest;
|
||||
|
||||
ARCHITECTURE behavior OF PrepareForShiftTest IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT PrepareForShift
|
||||
PORT(
|
||||
X : IN std_logic_vector(30 downto 0);
|
||||
Y : IN std_logic_vector(30 downto 0);
|
||||
DIFF_EXP : OUT std_logic_vector(8 downto 0);
|
||||
NEED_SWAP : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal X : std_logic_vector(30 downto 0) := (others => '0');
|
||||
signal Y : std_logic_vector(30 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal DIFF_EXP : std_logic_vector(8 downto 0);
|
||||
signal NEED_SWAP : std_logic;
|
||||
signal clock : std_logic;
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: PrepareForShift PORT MAP (
|
||||
X => X,
|
||||
Y => Y,
|
||||
DIFF_EXP => DIFF_EXP,
|
||||
NEED_SWAP => NEED_SWAP
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clock_process :process
|
||||
begin
|
||||
clock <= '0';
|
||||
wait for clock_period/2;
|
||||
clock <= '1';
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
test_proc: process
|
||||
begin
|
||||
X <= "00011100" & "00001110000000000000000";
|
||||
Y <= "00100011" & "00100000000000000000000";
|
||||
wait for clock_period;
|
||||
X <= "00110000" & "00000000111000000000000";
|
||||
Y <= "10110000" & "00000001111000000000000";
|
||||
wait for clock_period;
|
||||
X <= "00001000" & "00000011001100000000000";
|
||||
Y <= "00011000" & "00000000100000000001110";
|
||||
wait for clock_period;
|
||||
X <= "00001100" & "00000000000000000000000";
|
||||
Y <= "00001100" & "00000000000000000000000";
|
||||
wait for clock_period;
|
||||
X <= "00010010" & "00000000011001000100000";
|
||||
Y <= "00010010" & "00000010011000000000000";
|
||||
wait for clock_period;
|
||||
X <= "01011000" & "00000000100000000000000";
|
||||
Y <= "01011000" & "00000000000000000000000";
|
||||
wait for clock_period;
|
||||
X <= "00100110" & "00000000011100001000100";
|
||||
Y <= "00001010" & "00000000011100001000100";
|
||||
wait for clock_period;
|
||||
X <= "01111100" & "00000001110000000101010";
|
||||
Y <= "00000100" & "00000101110000100110000";
|
||||
wait for clock_period;
|
||||
wait for clock_period;
|
||||
X <= "00100000" & "00000110000000000000000";
|
||||
Y <= "00001000" & "00000000100100100100000";
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
END;
|
||||
BIN
PrepareForShiftTest_isim_beh.exe
Normal file
BIN
PrepareForShiftTest_isim_beh.exe
Normal file
Binary file not shown.
BIN
PrepareForShiftTest_isim_beh.wdb
Normal file
BIN
PrepareForShiftTest_isim_beh.wdb
Normal file
Binary file not shown.
@@ -1,7 +1,6 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
|
||||
entity ShiftRight48 is
|
||||
|
||||
port(
|
||||
@@ -18,7 +17,9 @@ architecture ShiftRightArch of ShiftRight48 is
|
||||
begin
|
||||
|
||||
asdf: process (N, PLACES)
|
||||
|
||||
begin
|
||||
|
||||
case PLACES is
|
||||
when "000000000" => RESULT <= N( 47 downto 0 );
|
||||
when "000000001" => RESULT <= "0" & N( 47 downto 1 );
|
||||
@@ -67,9 +68,10 @@ begin
|
||||
when "000101100" => RESULT <= "00000000000000000000000000000000000000000000" & N( 47 downto 44 );
|
||||
when "000101101" => RESULT <= "000000000000000000000000000000000000000000000" & N( 47 downto 45 );
|
||||
when "000101110" => RESULT <= "0000000000000000000000000000000000000000000000" & N( 47 downto 46 );
|
||||
when "000101111" => RESULT <= "00000000000000000000000000000000000000000000000" & N( 47 );
|
||||
when others => RESULT <= "000000000000000000000000000000000000000000000000";
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
end ShiftRightArch;
|
||||
|
||||
95
ShiftRight48Test.vhd
Normal file
95
ShiftRight48Test.vhd
Normal file
@@ -0,0 +1,95 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY ShiftRight48Test IS
|
||||
END ShiftRight48Test;
|
||||
|
||||
ARCHITECTURE behavior OF ShiftRight48Test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT ShiftRight48
|
||||
PORT(
|
||||
N : IN std_logic_vector(47 downto 0);
|
||||
PLACES : IN std_logic_vector(8 downto 0);
|
||||
RESULT : OUT std_logic_vector(47 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal N : std_logic_vector(47 downto 0) := (others => '0');
|
||||
signal PLACES : std_logic_vector(8 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal RESULT : std_logic_vector(47 downto 0);
|
||||
signal clock : std_logic;
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: ShiftRight48 PORT MAP (
|
||||
N => N,
|
||||
PLACES => PLACES,
|
||||
RESULT => RESULT
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clock_process :process
|
||||
begin
|
||||
clock <= '0';
|
||||
wait for clock_period/2;
|
||||
clock <= '1';
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
test_proc: process
|
||||
begin
|
||||
N <= "000000000011111000001110000000000000000000000000";
|
||||
PLACES <= "000000000"; --0
|
||||
wait for clock_period;
|
||||
N <= "000000000000001010000100000000000100000000000000";
|
||||
PLACES <= "000001000"; --8
|
||||
wait for clock_period;
|
||||
N <= "000000100000111101000000000000010000000000000000";
|
||||
PLACES <= "010011100"; --156
|
||||
wait for clock_period;
|
||||
N <= "000011100000000001111001101000000000000111110000";
|
||||
PLACES <= "000110000"; --48
|
||||
wait for clock_period;
|
||||
N <= "000000011111110000000001010101000110011000000000";
|
||||
PLACES <= "111111111"; --511
|
||||
wait for clock_period;
|
||||
N <= "000000111000000000011100000000000000011100000000";
|
||||
PLACES <= "000100100"; --36
|
||||
wait for clock_period;
|
||||
N <= "000000000000111110000000000111110000000000011111";
|
||||
PLACES <= "000001101"; --13
|
||||
wait for clock_period;
|
||||
N <= "000001000111100000001100000000111111111111111111";
|
||||
PLACES <= "000011111"; --31
|
||||
wait for clock_period;
|
||||
N <= "000000000011111111111111111111111000000000010001";
|
||||
PLACES <= "000000111"; --7
|
||||
wait for clock_period;
|
||||
N <= "111111111111111111111111111111111111111111111111";
|
||||
PLACES <= "001000000"; --64
|
||||
wait for clock_period;
|
||||
N <= "111111111111111111111111111111111111111111111111";
|
||||
PLACES <= "000101111"; --47
|
||||
wait for clock_period;
|
||||
N <= "000000000000000000000000000000000000000000000011";
|
||||
PLACES <= "000000001"; --1
|
||||
wait for clock_period;
|
||||
N <= "000000000000000000000011111000000000000000000000";
|
||||
PLACES <= "000000000"; --0
|
||||
wait for clock_period;
|
||||
N <= "000000000001111000000000000000000000000000000000";
|
||||
PLACES <= "000011011"; --27
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
END;
|
||||
BIN
ShiftRight48Test_isim_beh.exe
Normal file
BIN
ShiftRight48Test_isim_beh.exe
Normal file
Binary file not shown.
@@ -12,8 +12,8 @@ ARCHITECTURE behavior OF SpecialCasesTest IS
|
||||
PORT(
|
||||
X : IN std_logic_vector(31 downto 0);
|
||||
Y : IN std_logic_vector(31 downto 0);
|
||||
isNaN : OUT std_logic;
|
||||
isZero : OUT std_logic
|
||||
IS_NAN : OUT std_logic;
|
||||
IS_ZERO : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
@@ -23,10 +23,8 @@ ARCHITECTURE behavior OF SpecialCasesTest IS
|
||||
signal Y : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal isNaN : std_logic;
|
||||
signal isZero : std_logic;
|
||||
-- No clocks detected in port list. Replace clock below with
|
||||
-- appropriate port name
|
||||
signal IS_NAN : std_logic;
|
||||
signal IS_ZERO : std_logic;
|
||||
signal clock : std_logic;
|
||||
|
||||
|
||||
@@ -42,8 +40,8 @@ BEGIN
|
||||
uut: SpecialCasesCheck PORT MAP (
|
||||
X => X,
|
||||
Y => Y,
|
||||
isNaN => isNaN,
|
||||
isZero => isZero
|
||||
IS_NAN => IS_NAN,
|
||||
IS_ZERO => IS_ZERO
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
@@ -160,6 +158,6 @@ BEGIN
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
error <= (expectedNaN xor isNaN) or (expectedZero xor isZero);
|
||||
error <= (expectedNaN xor IS_NAN) or (expectedZero xor IS_ZERO);
|
||||
|
||||
END;
|
||||
|
||||
@@ -15,6 +15,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
|
||||
|
||||
signal X_FST_BIT : std_logic;
|
||||
signal Y_FST_BIT : std_logic;
|
||||
signal FILL : std_logic_vector(23 downto 0);
|
||||
signal N : std_logic_vector(47 downto 0);
|
||||
|
||||
component ShiftRight48 is
|
||||
|
||||
@@ -28,6 +30,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
|
||||
|
||||
begin
|
||||
|
||||
FILL <= (others => '0');
|
||||
|
||||
X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
|
||||
|
||||
variable X_FST_TMP : std_logic := '0';
|
||||
@@ -45,11 +49,12 @@ begin
|
||||
|
||||
end process;
|
||||
|
||||
--istanziare shifter
|
||||
SHIFTER : ShiftRight48
|
||||
port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT);
|
||||
N <= Y_FST_BIT & Y_IN(22 downto 0) & FILL;
|
||||
|
||||
X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000";
|
||||
SHIFTER : ShiftRight48
|
||||
port map (N => N, PLACES => DIFF_EXP, RESULT => Y_OUT);
|
||||
|
||||
--X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL;
|
||||
|
||||
end SumDataAdapterArch;
|
||||
|
||||
|
||||
104
SumDataAdapterTest.vhd
Normal file
104
SumDataAdapterTest.vhd
Normal file
@@ -0,0 +1,104 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
ENTITY SumDataAdapterTest IS
|
||||
END SumDataAdapterTest;
|
||||
|
||||
ARCHITECTURE behavior OF SumDataAdapterTest IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT SumDataAdapter
|
||||
PORT(
|
||||
X_IN : IN std_logic_vector(30 downto 0);
|
||||
Y_IN : IN std_logic_vector(30 downto 0);
|
||||
DIFF_EXP : IN std_logic_vector(8 downto 0);
|
||||
X_OUT : OUT std_logic_vector(47 downto 0);
|
||||
Y_OUT : OUT std_logic_vector(47 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal X_IN : std_logic_vector(30 downto 0) := (others => '0');
|
||||
signal Y_IN : std_logic_vector(30 downto 0) := (others => '0');
|
||||
signal DIFF_EXP : std_logic_vector(8 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal X_OUT : std_logic_vector(47 downto 0);
|
||||
signal Y_OUT : std_logic_vector(47 downto 0);
|
||||
signal clock : std_logic;
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: SumDataAdapter PORT MAP (
|
||||
X_IN => X_IN,
|
||||
Y_IN => Y_IN,
|
||||
DIFF_EXP => DIFF_EXP,
|
||||
X_OUT => X_OUT,
|
||||
Y_OUT => Y_OUT
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clock_process :process
|
||||
begin
|
||||
clock <= '0';
|
||||
wait for clock_period/2;
|
||||
clock <= '1';
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clock_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
test_process :process
|
||||
begin
|
||||
X_IN <= "111111110000010001000100000000";
|
||||
Y_IN <= "001001000000000010001000000000";
|
||||
DIFF_EXP <= "000000000"; --0
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000100000000001000000";
|
||||
Y_IN <= "000000000000001111111000000000";
|
||||
DIFF_EXP <= "000001000"; --8
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000000000111000000000";
|
||||
Y_IN <= "000010000000000000000000000111";
|
||||
DIFF_EXP <= "010011100"; --156
|
||||
wait for clock_period;
|
||||
X_IN <= "000000100000000000000000000000";
|
||||
Y_IN <= "000000001000000001111111111111";
|
||||
DIFF_EXP <= "000110000"; --48
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000000000000000010000";
|
||||
Y_IN <= "000000000000000000011100000000";
|
||||
DIFF_EXP <= "111111111"; --511
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000000000000000000000";
|
||||
Y_IN <= "000000000000011100000000000000";
|
||||
DIFF_EXP <= "000100100"; --36
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000000000000000000000";
|
||||
Y_IN <= "000000000000000000000000000000";
|
||||
DIFF_EXP <= "000001101"; --13
|
||||
wait for clock_period;
|
||||
X_IN <= "000000000000000001110001100100";
|
||||
Y_IN <= "000000000000000000000011110000";
|
||||
DIFF_EXP <= "000011111"; --31
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
END;
|
||||
55
SwapTest.vhd
55
SwapTest.vhd
@@ -1,10 +1,6 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY SwapTest IS
|
||||
END SwapTest;
|
||||
|
||||
@@ -24,16 +20,14 @@ ARCHITECTURE behavior OF SwapTest IS
|
||||
|
||||
|
||||
--Inputs
|
||||
signal X_IN : std_logic_vector(7 downto 0) := "01010101";
|
||||
signal Y_IN : std_logic_vector(7 downto 0) := "10101010";
|
||||
signal SW : std_logic := '1';
|
||||
signal X_IN : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal Y_IN : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal SW : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal X_OUT : std_logic_vector(7 downto 0);
|
||||
signal Y_OUT : std_logic_vector(7 downto 0);
|
||||
signal clock : std_logic;
|
||||
-- No clocks detected in port list. Replace clock below with
|
||||
-- appropriate port name
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
@@ -58,17 +52,40 @@ BEGIN
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
test_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clock_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
wait;
|
||||
X_IN <= "00110000";
|
||||
Y_IN <= "00010000";
|
||||
SW <= '0';
|
||||
wait for clock_period;
|
||||
X_IN <= "01100000";
|
||||
Y_IN <= "01110000";
|
||||
SW <= '1';
|
||||
wait for clock_period;
|
||||
X_IN <= "01101000";
|
||||
Y_IN <= "00110110";
|
||||
SW <= '1';
|
||||
wait for clock_period;
|
||||
X_IN <= "00111111";
|
||||
Y_IN <= "01000000";
|
||||
SW <= '0';
|
||||
wait for clock_period;
|
||||
X_IN <= "00101001";
|
||||
Y_IN <= "00101000";
|
||||
SW <= '1';
|
||||
wait for clock_period;
|
||||
X_IN <= "00000000";
|
||||
Y_IN <= "00000000";
|
||||
SW <= '1';
|
||||
wait for clock_period;
|
||||
X_IN <= "00110000";
|
||||
Y_IN <= "00110000";
|
||||
SW <= '0';
|
||||
wait for clock_period;
|
||||
X_IN <= "11111111";
|
||||
Y_IN <= "00000000";
|
||||
SW <= '1';
|
||||
wait for clock_period;
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
||||
Binary file not shown.
@@ -1,10 +1,6 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY TwoComplementTest IS
|
||||
END TwoComplementTest;
|
||||
|
||||
@@ -21,13 +17,11 @@ ARCHITECTURE behavior OF TwoComplementTest IS
|
||||
|
||||
|
||||
--Inputs
|
||||
signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000";
|
||||
signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal DIFF_EXP : std_logic_vector(7 downto 0);
|
||||
signal clock : std_logic;
|
||||
-- No clocks detected in port list. Replace clock below with
|
||||
-- appropriate port name
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
@@ -48,20 +42,6 @@ BEGIN
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
|
||||
wait for clock_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
test_process :process
|
||||
begin
|
||||
DIFF_EXP_C2 <= "01001110";
|
||||
|
||||
22
fuse.log
22
fuse.log
@@ -1,21 +1,11 @@
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
Number of CPUs detected in this system: 1
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 0
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 95308 KB
|
||||
Fuse CPU Usage: 2300 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
|
||||
Compiling architecture behavior of entity twocomplementtest
|
||||
Time Resolution for simulation is 1ps.
|
||||
Compiled 5 VHDL Units
|
||||
Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
|
||||
Fuse Memory Usage: 103960 KB
|
||||
Fuse CPU Usage: 2400 ms
|
||||
GCC CPU Usage: 1480 ms
|
||||
ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
|
||||
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
|
||||
|
||||
@@ -5,5 +5,11 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="error" file="HDLCompiler" num="410" delta="unknown" >"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has <arg fmt="%d" index="1">30</arg> elements ; expected <arg fmt="%d" index="2">31</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="error" file="Simulator" num="777" delta="unknown" >Static elaboration of top level VHDL design unit <arg fmt="%s" index="1">sumdataadaptertest</arg> in library <arg fmt="%s" index="2">work</arg> failed
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
||||
@@ -1 +1 @@
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest"
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj" "work.SumDataAdapterTest"
|
||||
|
||||
16
isim.log
16
isim.log
@@ -1,16 +0,0 @@
|
||||
ISim log file
|
||||
Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
----------------------------------------------------------------------
|
||||
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
This is a Full version of ISim.
|
||||
Time resolution is 1 ps
|
||||
# onerror resume
|
||||
# wave add /
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
Finished circuit initialization process.
|
||||
# exit 0
|
||||
Reference in New Issue
Block a user