From 0250f39c47c523c9ddf2c6d34b0c7f1a4ac71377 Mon Sep 17 00:00:00 2001 From: Giulio Date: Fri, 30 Aug 2019 19:24:54 +0200 Subject: [PATCH] Aggiunti test --- AddSubTest.vhd | 52 ++++++++-------- AddSubTest_isim_beh.exe | Bin 21792 -> 21792 bytes AddSubTest_isim_beh.wdb | Bin 16626 -> 0 bytes AdderTest.vhd | 43 ++++++------- ComparatorTest.vhd | 60 +++++++++++------- IEEE754Adder.xise | 84 +++++++++++++++++-------- OperationCheckTest.vhd | 68 ++++++++++++++++++++ OperationCheckTest_isim_beh.exe | Bin 0 -> 21792 bytes PrepareForShiftTest.vhd | 84 +++++++++++++++++++++++++ PrepareForShiftTest_isim_beh.exe | Bin 0 -> 21792 bytes PrepareForShiftTest_isim_beh.wdb | Bin 0 -> 22744 bytes ShiftRight.vhd | 6 +- ShiftRight48Test.vhd | 95 ++++++++++++++++++++++++++++ ShiftRight48Test_isim_beh.exe | Bin 0 -> 21792 bytes SpecialCasesTest.vhd | 16 +++-- SumDataAdapter.vhd | 11 +++- SumDataAdapterTest.vhd | 104 +++++++++++++++++++++++++++++++ SwapTest.vhd | 61 +++++++++++------- SwapTest_isim_beh.wdb | Bin 5597 -> 0 bytes TwoComplementTest.vhd | 24 +------ fuse.log | 22 ++----- fuse.xmsgs | 6 ++ fuseRelaunch.cmd | 2 +- isim.log | 16 ----- 24 files changed, 565 insertions(+), 189 deletions(-) delete mode 100644 AddSubTest_isim_beh.wdb create mode 100644 OperationCheckTest.vhd create mode 100644 OperationCheckTest_isim_beh.exe create mode 100644 PrepareForShiftTest.vhd create mode 100644 PrepareForShiftTest_isim_beh.exe create mode 100644 PrepareForShiftTest_isim_beh.wdb create mode 100644 ShiftRight48Test.vhd create mode 100644 ShiftRight48Test_isim_beh.exe create mode 100644 SumDataAdapterTest.vhd delete mode 100644 SwapTest_isim_beh.wdb delete mode 100644 isim.log diff --git a/AddSubTest.vhd b/AddSubTest.vhd index d3d071c..7968a63 100644 --- a/AddSubTest.vhd +++ b/AddSubTest.vhd @@ -13,9 +13,9 @@ ARCHITECTURE behavior OF AddSubTest IS PORT( X : IN std_logic_vector(7 downto 0); Y : IN std_logic_vector(7 downto 0); - isSub : IN std_logic; - result : OUT std_logic_vector(7 downto 0); - overflow : OUT std_logic + IS_SUB : IN std_logic; + RESULT : OUT std_logic_vector(7 downto 0); + OVERFLOW : OUT std_logic ); END COMPONENT; @@ -23,11 +23,11 @@ ARCHITECTURE behavior OF AddSubTest IS --Inputs signal X : std_logic_vector(7 downto 0) := (others => '0'); signal Y : std_logic_vector(7 downto 0) := (others => '0'); - signal isSub : std_logic := '0'; + signal IS_SUB : std_logic := '0'; --Outputs - signal result : std_logic_vector(7 downto 0); - signal overflow : std_logic; + signal RESULT : std_logic_vector(7 downto 0); + signal OVERFLOW : std_logic; signal clock: std_logic; constant clock_period : time := 10 ns; @@ -38,9 +38,9 @@ BEGIN uut: AddSub PORT MAP ( X => X, Y => Y, - isSub => isSub, - result => result, - overflow => overflow + IS_SUB => IS_SUB, + RESULT => RESULT, + OVERFLOW => OVERFLOW ); -- Clock process definitions @@ -57,70 +57,70 @@ BEGIN begin X <= "00110011"; Y <= "11001100"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "10010111"; Y <= "11100011"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "10000101"; Y <= "01111011"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "11111111"; Y <= "11111111"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "00101011"; Y <= "00101010"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "11111111"; Y <= "11111111"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "10000000"; Y <= "10000000"; - isSub <= '0'; + IS_SUB <= '0'; wait for clock_period; X <= "00000000"; Y <= "11111111"; - isSub <= '0'; + IS_SUB <= '0'; X <= "00110011"; Y <= "11001100"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "10010111"; Y <= "11100011"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "10000101"; Y <= "01111011"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "11111111"; Y <= "11111111"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "00101011"; Y <= "00101010"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "11111111"; Y <= "11111111"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "10000000"; Y <= "10000000"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "00000000"; Y <= "11111111"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; X <= "11111111"; Y <= "00000000"; - isSub <= '1'; + IS_SUB <= '1'; wait for clock_period; end process; diff --git a/AddSubTest_isim_beh.exe b/AddSubTest_isim_beh.exe index 3209988d8d84424c4d5c423f8f5aaa98e3cf50c8..11ae4f70553f0c5d3994a18a93c772b43d96d96f 100755 GIT binary patch delta 2813 zcmZ8ieQaCR6~EUXi4%W2cAlSG*UygQe63FGq=~&IsZ%?NT^u!q6a=D*^HpjVoUV3D z`Pdo+2pOxZ=#kKnsFu-bl&&42E@DDrqY5K1seb^~)Jd?m>ohrnPGxLWVGY^2&+nzy zj`Vxy+~4oqbI&_|esAG4T{uk_XVjH3k!OVhCAv}n7gbTqe%%n{i^ovVE{OAL4!QTdV6n3~uRYz(hMRryU zY|^4y@+QeE&{KpRVV1a!=sAQ_T5BZlK<`E9q_tA=ZRmYcTt&!s!sDU=QIF6fHY41K zPQ(^O7s7y$tr>%E#0Eqkq7^=&E_w;5YP_WnyE9{Z!h*A>q^jL~L#lUMnurEks$Ggs73`?? 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Replace clock below with - -- appropriate port name - signal clock: std_logic; + signal RESULT : std_logic_vector(47 downto 0); + signal OVERFLOW : std_logic; + signal clock : std_logic; constant clock_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) - uut: Adder PORT MAP ( + uut: CarryLookAhead PORT MAP ( X => X, Y => Y, - carry_in => carry_in, - result => result, - carry_out => carry_out + OP => OP, + RESULT => RESULT, + OVERFLOW => OVERFLOW ); -- Clock process definitions @@ -52,8 +50,11 @@ BEGIN clock <= '1'; wait for clock_period/2; end process; - - x <= "00010101"; - y <= "00001110"; + + test_proc: process + begin + --test + wait for clock_period; + end process; END; diff --git a/ComparatorTest.vhd b/ComparatorTest.vhd index 78185cb..f3bd1a8 100644 --- a/ComparatorTest.vhd +++ b/ComparatorTest.vhd @@ -11,21 +11,19 @@ ARCHITECTURE behavior OF ComparatorTest IS COMPONENT Comparator PORT( - xT : IN std_logic_vector(7 downto 0); - yT : IN std_logic_vector(7 downto 0); - needSwap : OUT std_logic + X_MANT : IN std_logic_vector(7 downto 0); + Y_MANT : IN std_logic_vector(7 downto 0); + NEED_SWAP : OUT std_logic ); END COMPONENT; --Inputs - signal xT : std_logic_vector(7 downto 0) := "11111111"; - signal yT : std_logic_vector(7 downto 0) := "11111111"; + signal X_MANT : std_logic_vector(7 downto 0) := (others => '0'); + signal Y_MANT : std_logic_vector(7 downto 0) := (others => '0'); --Outputs - signal needSwap : std_logic; - -- No clocks detected in port list. Replace clock below with - -- appropriate port name + signal NEED_SWAP : std_logic; signal clock: std_logic; constant clock_period : time := 10 ns; @@ -34,9 +32,9 @@ BEGIN -- Instantiate the Unit Under Test (UUT) uut: Comparator PORT MAP ( - xT => xT, - yT => yT, - needSwap => needSwap + X_MANT => X_MANT, + Y_MANT => Y_MANT, + NEED_SWAP => NEED_SWAP ); -- Clock process definitions @@ -48,18 +46,32 @@ BEGIN wait for clock_period/2; end process; - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100 ns. - wait for 100 ns; - - wait for clock_period*10; - - -- insert stimulus here - - wait; - end process; + test_proc: process + begin + X_MANT <= "00000000"; + Y_MANT <= "00000000"; + wait for clock_period; + X_MANT <= "01011010"; + Y_MANT <= "01100000"; + wait for clock_period; + X_MANT <= "00111100"; + Y_MANT <= "10000100"; + wait for clock_period; + X_MANT <= "10000000"; + Y_MANT <= "01111111"; + wait for clock_period; + X_MANT <= "01110100"; + Y_MANT <= "01101000"; + wait for clock_period; + X_MANT <= "01111111"; + Y_MANT <= "10000000"; + wait for clock_period; + X_MANT <= "10101010"; + Y_MANT <= "01010101"; + wait for clock_period; + X_MANT <= "01010101"; + Y_MANT <= "10101010"; + wait for clock_period; + end process; END; diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise index a431073..9490c6c 100644 --- a/IEEE754Adder.xise +++ b/IEEE754Adder.xise @@ -43,7 +43,7 @@ - + @@ -53,7 +53,7 @@ - + @@ -66,7 +66,7 @@ - + @@ -74,41 +74,71 @@ - + - - + + - - + + - + - + - - + + - - + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -229,9 +259,9 @@ - - - + + + @@ -300,7 +330,7 @@ - + @@ -315,10 +345,10 @@ - - - - + + + + @@ -367,8 +397,8 @@ - - + + @@ -387,7 +417,7 @@ - + @@ -443,7 +473,7 @@ - + diff --git a/OperationCheckTest.vhd b/OperationCheckTest.vhd new file mode 100644 index 0000000..f31d4eb --- /dev/null +++ b/OperationCheckTest.vhd @@ -0,0 +1,68 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY OperationCheckTest IS +END OperationCheckTest; + +ARCHITECTURE behavior OF OperationCheckTest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT OperationCheck + PORT( + X_SIGN : IN std_logic; + Y_SIGN : IN std_logic; + OP : OUT std_logic; + RES_SIGN : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal X_SIGN : std_logic := '0'; + signal Y_SIGN : std_logic := '0'; + + --Outputs + signal OP : std_logic; + signal RES_SIGN : std_logic; + signal clock : std_logic; + + constant clock_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: OperationCheck PORT MAP ( + X_SIGN => X_SIGN, + Y_SIGN => Y_SIGN, + OP => OP, + RES_SIGN => RES_SIGN + ); + + -- Clock process definitions + clock_process :process + begin + clock <= '0'; + wait for clock_period/2; + clock <= '1'; + wait for clock_period/2; + end process; + + + test_proc: process + begin + X_SIGN <= '0'; + Y_SIGN <= '0'; + wait for clock_period; + X_SIGN <= '0'; + Y_SIGN <= '1'; + wait for clock_period; + X_SIGN <= '1'; + Y_SIGN <= '0'; + wait for clock_period; + X_SIGN <= '1'; + Y_SIGN <= '1'; + wait for clock_period; + end process; + +END; diff --git a/OperationCheckTest_isim_beh.exe b/OperationCheckTest_isim_beh.exe new file mode 100644 index 0000000000000000000000000000000000000000..11ae4f70553f0c5d3994a18a93c772b43d96d96f GIT binary patch literal 21792 zcmeHPe|%KMwV(WgltMNjXatliE^QFAWFcUJ3GT8RxN8@T5G?x8-DR^$R+HVhKOk5> z8k$78T^ITI{8(S#r?0&J(7wL*mG)T#YB3O!6zvbCYHj_6zwe4DR?9<*?)#p(Gs$Iz zzJ4D5XC|L}&zv*ooH=vm%-or|cXLO*cWHiJ9+N4bEoOu%We!d2MR14&3 z5?)SnWb1Pdjsp65W*C0apsSN)O$sNFc_dft(hqqfmCU9@j{z5^KH z4gyT!_Yuf_0b0Wwi6+W#y2@bKbd`f=B&;>aOhPGlE#%0~e>6!u=eC8{Ev%Z`)>P3J zjwCxPI;$5}EUdD{qqce6{!%EUCN5jCnyZ%n_=2ct7T^+G3a$ybWO9hi<$%O98`qV% zzKn~K#Q^LIz-nBTxW?gHgv*JG+BXjux#2uqlqTV#_RhpL7uO72lxlEYjB7C=NH$z{ zp8Lmcr^nOjGP0eLIvJTM0vRhH`G^wvhJ00qYa%X6({WvZ>movsq~E6^Z^bp9h)6UZ zD9yq3C7v_l?n2}*#dSU|3egH&m*AR@YXPn*TqU?_vu>uSI zZvSa)bI_29&^%VeAN38T0??@+Wcseid=t=2m;GDE^^`H?dcVPW(g61g`iEYFF5~zK z6r1%-6XWtZUhjC;aG8TEAYW5@4)#xi7v+3qP#M#?{tH-_XcthPsvtO#dgxleK@c56 z{h%0>)9&QQGtvJObhDjziwc4{bSe8`4t<(v@VzZ!@!O!WkUycj@z8wB>@IS>#zK9b! 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"000000000000000000000000000000000000000000000000"; end case; + end process; - end ShiftRightArch; diff --git a/ShiftRight48Test.vhd b/ShiftRight48Test.vhd new file mode 100644 index 0000000..3b73171 --- /dev/null +++ b/ShiftRight48Test.vhd @@ -0,0 +1,95 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY ShiftRight48Test IS +END ShiftRight48Test; + +ARCHITECTURE behavior OF ShiftRight48Test IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT ShiftRight48 + PORT( + N : IN std_logic_vector(47 downto 0); + PLACES : IN std_logic_vector(8 downto 0); + RESULT : OUT std_logic_vector(47 downto 0) + ); + END COMPONENT; + + + --Inputs + signal N : std_logic_vector(47 downto 0) := (others => '0'); + signal PLACES : std_logic_vector(8 downto 0) := (others => '0'); + + --Outputs + signal RESULT : std_logic_vector(47 downto 0); + signal clock : std_logic; + + constant clock_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: ShiftRight48 PORT MAP ( + N => N, + PLACES => PLACES, + RESULT => RESULT + ); + + -- Clock process definitions + clock_process :process + begin + clock <= '0'; + wait for clock_period/2; + clock <= '1'; + wait for clock_period/2; + end process; + + + test_proc: process + begin + N <= "000000000011111000001110000000000000000000000000"; + PLACES <= "000000000"; --0 + wait for clock_period; + N <= "000000000000001010000100000000000100000000000000"; + PLACES <= "000001000"; --8 + wait for clock_period; + N <= "000000100000111101000000000000010000000000000000"; + PLACES <= "010011100"; --156 + wait for clock_period; + N <= "000011100000000001111001101000000000000111110000"; + PLACES <= "000110000"; --48 + wait for clock_period; + N <= "000000011111110000000001010101000110011000000000"; + PLACES <= "111111111"; --511 + wait for clock_period; + N <= "000000111000000000011100000000000000011100000000"; + PLACES <= "000100100"; --36 + wait for clock_period; + N <= "000000000000111110000000000111110000000000011111"; + PLACES <= "000001101"; --13 + wait for clock_period; + N <= "000001000111100000001100000000111111111111111111"; + PLACES <= "000011111"; --31 + wait for clock_period; + N <= "000000000011111111111111111111111000000000010001"; + PLACES <= "000000111"; --7 + wait for clock_period; + N <= "111111111111111111111111111111111111111111111111"; + PLACES <= "001000000"; --64 + wait for clock_period; + N <= "111111111111111111111111111111111111111111111111"; + PLACES <= "000101111"; --47 + wait for clock_period; + N <= "000000000000000000000000000000000000000000000011"; + PLACES <= "000000001"; --1 + wait for clock_period; + N <= "000000000000000000000011111000000000000000000000"; + PLACES <= "000000000"; --0 + wait for clock_period; + N <= "000000000001111000000000000000000000000000000000"; + PLACES <= "000011011"; --27 + wait for clock_period; + end process; + +END; diff --git a/ShiftRight48Test_isim_beh.exe b/ShiftRight48Test_isim_beh.exe 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Replace clock below with - -- appropriate port name + signal IS_NAN : std_logic; + signal IS_ZERO : std_logic; signal clock : std_logic; @@ -42,8 +40,8 @@ BEGIN uut: SpecialCasesCheck PORT MAP ( X => X, Y => Y, - isNaN => isNaN, - isZero => isZero + IS_NAN => IS_NAN, + IS_ZERO => IS_ZERO ); -- Clock process definitions @@ -160,6 +158,6 @@ BEGIN wait for clock_period; end process; - error <= (expectedNaN xor isNaN) or (expectedZero xor isZero); + error <= (expectedNaN xor IS_NAN) or (expectedZero xor IS_ZERO); END; diff --git a/SumDataAdapter.vhd b/SumDataAdapter.vhd index 57586f2..c77bbaa 100644 --- a/SumDataAdapter.vhd +++ b/SumDataAdapter.vhd @@ -15,6 +15,8 @@ architecture SumDataAdapterArch of SumDataAdapter is signal X_FST_BIT : std_logic; signal Y_FST_BIT : std_logic; + signal FILL : std_logic_vector(23 downto 0); + signal N : std_logic_vector(47 downto 0); component ShiftRight48 is @@ -28,6 +30,8 @@ architecture SumDataAdapterArch of SumDataAdapter is begin + FILL <= (others => '0'); + X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN) variable X_FST_TMP : std_logic := '0'; @@ -45,11 +49,12 @@ begin end process; - --istanziare shifter + N <= Y_FST_BIT & Y_IN(22 downto 0) & FILL; + SHIFTER : ShiftRight48 - port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT); + port map (N => N, PLACES => DIFF_EXP, RESULT => Y_OUT); - X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000"; + --X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL; end SumDataAdapterArch; diff --git a/SumDataAdapterTest.vhd b/SumDataAdapterTest.vhd new file mode 100644 index 0000000..3ee3dc4 --- /dev/null +++ b/SumDataAdapterTest.vhd @@ -0,0 +1,104 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY SumDataAdapterTest IS +END SumDataAdapterTest; + +ARCHITECTURE behavior OF SumDataAdapterTest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT SumDataAdapter + PORT( + X_IN : IN std_logic_vector(30 downto 0); + Y_IN : IN std_logic_vector(30 downto 0); + DIFF_EXP : IN std_logic_vector(8 downto 0); + X_OUT : OUT std_logic_vector(47 downto 0); + Y_OUT : OUT std_logic_vector(47 downto 0) + ); + END COMPONENT; + + + --Inputs + signal X_IN : std_logic_vector(30 downto 0) := (others => '0'); + signal Y_IN : std_logic_vector(30 downto 0) := (others => '0'); + signal DIFF_EXP : std_logic_vector(8 downto 0) := (others => '0'); + + --Outputs + signal X_OUT : std_logic_vector(47 downto 0); + signal Y_OUT : std_logic_vector(47 downto 0); + signal clock : std_logic; + + constant clock_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: SumDataAdapter PORT MAP ( + X_IN => X_IN, + Y_IN => Y_IN, + DIFF_EXP => DIFF_EXP, + X_OUT => X_OUT, + Y_OUT => Y_OUT + ); + + -- Clock process definitions + clock_process :process + begin + clock <= '0'; + wait for clock_period/2; + clock <= '1'; + wait for clock_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for clock_period*10; + + -- insert stimulus here + + wait; + end process; + + test_process :process + begin + X_IN <= "111111110000010001000100000000"; + Y_IN <= "001001000000000010001000000000"; + DIFF_EXP <= "000000000"; --0 + wait for clock_period; + X_IN <= "000000000000100000000001000000"; + Y_IN <= "000000000000001111111000000000"; + DIFF_EXP <= "000001000"; --8 + wait for clock_period; + X_IN <= "000000000000000000111000000000"; + Y_IN <= "000010000000000000000000000111"; + DIFF_EXP <= "010011100"; --156 + wait for clock_period; + X_IN <= "000000100000000000000000000000"; + Y_IN <= "000000001000000001111111111111"; + DIFF_EXP <= "000110000"; --48 + wait for clock_period; + X_IN <= "000000000000000000000000010000"; + Y_IN <= "000000000000000000011100000000"; + DIFF_EXP <= "111111111"; --511 + wait for clock_period; + X_IN <= "000000000000000000000000000000"; + Y_IN <= "000000000000011100000000000000"; + DIFF_EXP <= "000100100"; --36 + wait for clock_period; + X_IN <= "000000000000000000000000000000"; + Y_IN <= "000000000000000000000000000000"; + DIFF_EXP <= "000001101"; --13 + wait for clock_period; + X_IN <= "000000000000000001110001100100"; + Y_IN <= "000000000000000000000011110000"; + DIFF_EXP <= "000011111"; --31 + wait for clock_period; + end process; + +END; diff --git a/SwapTest.vhd b/SwapTest.vhd index b369f4c..cdf96dc 100644 --- a/SwapTest.vhd +++ b/SwapTest.vhd @@ -1,10 +1,6 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---USE ieee.numeric_std.ALL; - + ENTITY SwapTest IS END SwapTest; @@ -24,16 +20,14 @@ ARCHITECTURE behavior OF SwapTest IS --Inputs - signal X_IN : std_logic_vector(7 downto 0) := "01010101"; - signal Y_IN : std_logic_vector(7 downto 0) := "10101010"; - signal SW : std_logic := '1'; + signal X_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal Y_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal SW : std_logic := '0'; --Outputs signal X_OUT : std_logic_vector(7 downto 0); signal Y_OUT : std_logic_vector(7 downto 0); signal clock : std_logic; - -- No clocks detected in port list. Replace clock below with - -- appropriate port name constant clock_period : time := 10 ns; @@ -58,17 +52,40 @@ BEGIN end process; - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100 ns. - wait for 100 ns; - - wait for clock_period*10; - - -- insert stimulus here - - wait; - end process; + test_proc: process + begin + X_IN <= "00110000"; + Y_IN <= "00010000"; + SW <= '0'; + wait for clock_period; + X_IN <= "01100000"; + Y_IN <= "01110000"; + SW <= '1'; + wait for clock_period; + X_IN <= "01101000"; + Y_IN <= "00110110"; + SW <= '1'; + wait for clock_period; + X_IN <= "00111111"; + Y_IN <= "01000000"; + SW <= '0'; + wait for clock_period; + X_IN <= "00101001"; + Y_IN <= "00101000"; + SW <= '1'; + wait for clock_period; + X_IN <= "00000000"; + Y_IN <= "00000000"; + SW <= '1'; + wait for clock_period; + X_IN <= "00110000"; + Y_IN <= "00110000"; + SW <= '0'; + wait for clock_period; + X_IN <= "11111111"; + Y_IN <= "00000000"; + SW <= '1'; + wait for clock_period; + end process; END; diff --git a/SwapTest_isim_beh.wdb b/SwapTest_isim_beh.wdb deleted file mode 100644 index 155220c4e425f60d029a3d657d06854a66e0fccd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 5597 zcmeH~Pi)jh6vqb@#Xmq1L=dD~s1yYH>q05CAeKT6RTN?+5Di(jyFc2E+uhCnc1!6& z@Pr{6iAOYw5jEjpNKnH;jTa4i^1wj}F?eg@K{S|{Xw>iLw=?ap>k=ve^EIXI0l0*KmQZyTodKr_?CQI<-4NN)TtDpvkL2VW1iQb z`|hdW@_oj<$H3Ajgww*E6?3eLN;yH8{{sT^Kpqm#PcKH{8C#zdl=K)xmN5n_FCEG^{8We&;FC`}I5Su4*Q z;yhwGtO*W$axtEic~{0#>tj!A<@rP$9y$84uWmlf&E@$@!DW`izShcfL7e55!=Ac4 z%-`ktS)4~LN5`*b9u~2}a_+Sp=EfRbo`NPfUAE+~e3WY})~Eh_PxvInkweV8p8`p6 zp!t@zk1Sk2Oa8e6{#F~OUI<-mt}yQUR_nTp=guw=xlvdptPOitz9pK}6HsF(tPgRT zIg;mP^*<&s2H!mr?S~&OKIXe3o^|Hak;bMa`w>FKg#7kLpsIfK8G^{hlJWhx!fhl z7IC@r;kt9n-bT4G*+`GL9nx@F6Pj-=%59L1>=2jp4TrY`sh-1P`8aR8#N|DKd%u9d zWeit`rE157cf?&OEoFEu(bV2?;eRZ|gx?fgB@Jhe)zmr4{a$uV_)DZ_X}G*CXlfVb zj>?V+Q#FVu4QH;^@S@y5WXFV=; zjpDABhRZh!mo-MYPg`z_xN8)H%X(KJs$UJE2wxIo-E~?fjEzlan+c zcQtf#n+%71i2Kf2tGl}=(`KGa1jgbFG}$(LvD~()`wH8>-Z@hz#J;iN-*Vg&jDv7a zZj{YB5avo=XD_^P?(Af2`obHXcPTuR*K0FgbbU9=cIz$F|2kp))%IsUOst2qS+5g! z2C-e+?ImXiac9tdXT;$WM-xXANAn({nJ1cBqp1~|yC2QDLnCesH#X;SKsYUj0rHoeiVK9>yt0N2I=VD;cou2PJejj(@WF6f&8HFWdh&p&m?oXjMvlM z-MwyY>*jRYFM7QPl7;8|pwv7xkTzbvQ1bRr z`(98=C$jneOeztNx3yL}Uvr$0M$dBC)imvDGEIAg79lP?FYFe!3)_TMO=g^)81hr4 zd@=O=zy6hp+U~u4Ldx?eTUg*_ZVvhC`RB zbXD@iIHk%r&KapivQEolp8sKuJ58dLFI0X4ZGK6cZ^jyZ{y=glqbd(4GC6aQpWuLu ze7Pix-&8iAda?4GDEP%pK5a^wLEr2TOd&A2z?1_s7?{9MnL+g)h-_GRR>t?QVix@% zpDmX%`CMhr#_KC*vS}~t_a{>agG{`|+u6LjCEnK39$(`XOZ%^V5|g>K&6O|O#_(7x zmoHggYDleof~_8Jj<|Ms1j<@4Ur6|~xtJQbdR_W5rBuG0E168L>5N0 '0'); --Outputs signal DIFF_EXP : std_logic_vector(7 downto 0); signal clock : std_logic; - -- No clocks detected in port list. Replace clock below with - -- appropriate port name constant clock_period : time := 10 ns; @@ -47,20 +41,6 @@ BEGIN clock <= '1'; wait for clock_period/2; end process; - - - -- Stimulus process - stim_proc: process - begin - -- hold reset state for 100 ns. - wait for 100 ns; - - wait for clock_period*10; - - -- insert stimulus here - - wait; - end process; test_process :process begin diff --git a/fuse.log b/fuse.log index b6e5b65..7286430 100644 --- a/fuse.log +++ b/fuse.log @@ -1,21 +1,11 @@ -Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest +Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest ISim P.20160913 (signature 0xfbc00daa) Number of CPUs detected in this system: 1 Turning on mult-threading, number of parallel sub-compilation jobs: 0 Determining compilation order of HDL files -Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work -Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work Starting static elaboration -Completed static elaboration -Fuse Memory Usage: 95308 KB -Fuse CPU Usage: 2300 ms -Compiling package standard -Compiling package std_logic_1164 -Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\] -Compiling architecture behavior of entity twocomplementtest -Time Resolution for simulation is 1ps. -Compiled 5 VHDL Units -Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -Fuse Memory Usage: 103960 KB -Fuse CPU Usage: 2400 ms -GCC CPU Usage: 1480 ms +ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31 +ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed diff --git a/fuse.xmsgs b/fuse.xmsgs index f84336a..ed9858d 100644 --- a/fuse.xmsgs +++ b/fuse.xmsgs @@ -5,5 +5,11 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> +"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31 + + +Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed + + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd index 07c2c4c..609200b 100644 --- a/fuseRelaunch.cmd +++ b/fuseRelaunch.cmd @@ -1 +1 @@ --intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest" +-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj" "work.SumDataAdapterTest" diff --git a/isim.log b/isim.log deleted file mode 100644 index e1e823f..0000000 --- a/isim.log +++ /dev/null @@ -1,16 +0,0 @@ -ISim log file -Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb -ISim P.20160913 (signature 0xfbc00daa) ----------------------------------------------------------------------- -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. - - ----------------------------------------------------------------------- -This is a Full version of ISim. -Time resolution is 1 ps -# onerror resume -# wave add / -# run 1000 ns -Simulator is doing circuit initialization process. -Finished circuit initialization process. -# exit 0