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Aggiunti test

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This commit is contained in:
Giulio
2019-08-30 19:24:54 +02:00
parent d077d1fe84
commit 0250f39c47
24 changed files with 565 additions and 189 deletions
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52
AddSubTest.vhd
View File

@@ -13,9 +13,9 @@ ARCHITECTURE behavior OF AddSubTest IS
PORT( PORT(
X : IN std_logic_vector(7 downto 0); X : IN std_logic_vector(7 downto 0);
Y : IN std_logic_vector(7 downto 0); Y : IN std_logic_vector(7 downto 0);
isSub : IN std_logic; IS_SUB : IN std_logic;
result : OUT std_logic_vector(7 downto 0); RESULT : OUT std_logic_vector(7 downto 0);
overflow : OUT std_logic OVERFLOW : OUT std_logic
); );
END COMPONENT; END COMPONENT;
@@ -23,11 +23,11 @@ ARCHITECTURE behavior OF AddSubTest IS
--Inputs --Inputs
signal X : std_logic_vector(7 downto 0) := (others => '0'); signal X : std_logic_vector(7 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0) := (others => '0'); signal Y : std_logic_vector(7 downto 0) := (others => '0');
signal isSub : std_logic := '0'; signal IS_SUB : std_logic := '0';
--Outputs --Outputs
signal result : std_logic_vector(7 downto 0); signal RESULT : std_logic_vector(7 downto 0);
signal overflow : std_logic; signal OVERFLOW : std_logic;
signal clock: std_logic; signal clock: std_logic;
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
@@ -38,9 +38,9 @@ BEGIN
uut: AddSub PORT MAP ( uut: AddSub PORT MAP (
X => X, X => X,
Y => Y, Y => Y,
isSub => isSub, IS_SUB => IS_SUB,
result => result, RESULT => RESULT,
overflow => overflow OVERFLOW => OVERFLOW
); );
-- Clock process definitions -- Clock process definitions
@@ -57,70 +57,70 @@ BEGIN
begin begin
X <= "00110011"; X <= "00110011";
Y <= "11001100"; Y <= "11001100";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "10010111"; X <= "10010111";
Y <= "11100011"; Y <= "11100011";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "10000101"; X <= "10000101";
Y <= "01111011"; Y <= "01111011";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "11111111"; X <= "11111111";
Y <= "11111111"; Y <= "11111111";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "00101011"; X <= "00101011";
Y <= "00101010"; Y <= "00101010";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "11111111"; X <= "11111111";
Y <= "11111111"; Y <= "11111111";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "10000000"; X <= "10000000";
Y <= "10000000"; Y <= "10000000";
isSub <= '0'; IS_SUB <= '0';
wait for clock_period; wait for clock_period;
X <= "00000000"; X <= "00000000";
Y <= "11111111"; Y <= "11111111";
isSub <= '0'; IS_SUB <= '0';
X <= "00110011"; X <= "00110011";
Y <= "11001100"; Y <= "11001100";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "10010111"; X <= "10010111";
Y <= "11100011"; Y <= "11100011";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "10000101"; X <= "10000101";
Y <= "01111011"; Y <= "01111011";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "11111111"; X <= "11111111";
Y <= "11111111"; Y <= "11111111";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "00101011"; X <= "00101011";
Y <= "00101010"; Y <= "00101010";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "11111111"; X <= "11111111";
Y <= "11111111"; Y <= "11111111";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "10000000"; X <= "10000000";
Y <= "10000000"; Y <= "10000000";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "00000000"; X <= "00000000";
Y <= "11111111"; Y <= "11111111";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
X <= "11111111"; X <= "11111111";
Y <= "00000000"; Y <= "00000000";
isSub <= '1'; IS_SUB <= '1';
wait for clock_period; wait for clock_period;
end process; end process;

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AddSubTest_isim_beh.exe
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AddSubTest_isim_beh.wdb
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41
AdderTest.vhd
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@@ -8,40 +8,38 @@ ARCHITECTURE behavior OF AdderTest IS
-- Component Declaration for the Unit Under Test (UUT) -- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder COMPONENT CarryLookAhead
PORT( PORT(
X : IN std_logic_vector(7 downto 0); X : IN std_logic_vector(47 downto 0);
Y : IN std_logic_vector(7 downto 0); Y : IN std_logic_vector(47 downto 0);
carry_in : IN std_logic; OP : IN std_logic;
result : OUT std_logic_vector(7 downto 0); RESULT : OUT std_logic_vector(47 downto 0);
carry_out : OUT std_logic OVERFLOW : OUT std_logic
); );
END COMPONENT; END COMPONENT;
--Inputs --Inputs
signal X : std_logic_vector(7 downto 0) := (others => '0'); signal X : std_logic_vector(47 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0) := (others => '0'); signal Y : std_logic_vector(47 downto 0) := (others => '0');
signal carry_in : std_logic := '0'; signal OP : std_logic := '0';
--Outputs --Outputs
signal result : std_logic_vector(7 downto 0); signal RESULT : std_logic_vector(47 downto 0);
signal carry_out : std_logic; signal OVERFLOW : std_logic;
-- No clocks detected in port list. Replace clock below with signal clock : std_logic;
-- appropriate port name
signal clock: std_logic;
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
BEGIN BEGIN
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: Adder PORT MAP ( uut: CarryLookAhead PORT MAP (
X => X, X => X,
Y => Y, Y => Y,
carry_in => carry_in, OP => OP,
result => result, RESULT => RESULT,
carry_out => carry_out OVERFLOW => OVERFLOW
); );
-- Clock process definitions -- Clock process definitions
@@ -53,7 +51,10 @@ BEGIN
wait for clock_period/2; wait for clock_period/2;
end process; end process;
x <= "00010101"; test_proc: process
y <= "00001110"; begin
--test
wait for clock_period;
end process;
END; END;

58
ComparatorTest.vhd
View File

@@ -11,21 +11,19 @@ ARCHITECTURE behavior OF ComparatorTest IS
COMPONENT Comparator COMPONENT Comparator
PORT( PORT(
xT : IN std_logic_vector(7 downto 0); X_MANT : IN std_logic_vector(7 downto 0);
yT : IN std_logic_vector(7 downto 0); Y_MANT : IN std_logic_vector(7 downto 0);
needSwap : OUT std_logic NEED_SWAP : OUT std_logic
); );
END COMPONENT; END COMPONENT;
--Inputs --Inputs
signal xT : std_logic_vector(7 downto 0) := "11111111"; signal X_MANT : std_logic_vector(7 downto 0) := (others => '0');
signal yT : std_logic_vector(7 downto 0) := "11111111"; signal Y_MANT : std_logic_vector(7 downto 0) := (others => '0');
--Outputs --Outputs
signal needSwap : std_logic; signal NEED_SWAP : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock: std_logic; signal clock: std_logic;
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
@@ -34,9 +32,9 @@ BEGIN
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: Comparator PORT MAP ( uut: Comparator PORT MAP (
xT => xT, X_MANT => X_MANT,
yT => yT, Y_MANT => Y_MANT,
needSwap => needSwap NEED_SWAP => NEED_SWAP
); );
-- Clock process definitions -- Clock process definitions
@@ -48,18 +46,32 @@ BEGIN
wait for clock_period/2; wait for clock_period/2;
end process; end process;
test_proc: process
-- Stimulus process
stim_proc: process
begin begin
-- hold reset state for 100 ns. X_MANT <= "00000000";
wait for 100 ns; Y_MANT <= "00000000";
wait for clock_period;
wait for clock_period*10; X_MANT <= "01011010";
Y_MANT <= "01100000";
-- insert stimulus here wait for clock_period;
X_MANT <= "00111100";
wait; Y_MANT <= "10000100";
end process; wait for clock_period;
X_MANT <= "10000000";
Y_MANT <= "01111111";
wait for clock_period;
X_MANT <= "01110100";
Y_MANT <= "01101000";
wait for clock_period;
X_MANT <= "01111111";
Y_MANT <= "10000000";
wait for clock_period;
X_MANT <= "10101010";
Y_MANT <= "01010101";
wait for clock_period;
X_MANT <= "01010101";
Y_MANT <= "10101010";
wait for clock_period;
end process;
END; END;

84
IEEE754Adder.xise
View File

@@ -43,7 +43,7 @@
</file> </file>
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -53,7 +53,7 @@
</file> </file>
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -66,7 +66,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
</file> </file>
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
@@ -74,41 +74,71 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
</file> </file>
<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="179"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="179"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="179"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="179"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="179"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="179"/>
</file> </file>
<file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="244"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="255"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="256"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="266"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="266"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="266"/>
</file>
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="274"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="274"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="OperationCheckTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="276"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="276"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="276"/>
</file>
<file xil_pn:name="PrepareForShiftTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="277"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="277"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="277"/>
</file>
<file xil_pn:name="ShiftRight48Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="279"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="279"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
</file>
</files> </files>
<properties> <properties>
@@ -229,9 +259,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PrepareForShift|PrepareForShiftArch" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SumDataAdapter|SumDataAdapterArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="PrepareForShift.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="SumDataAdapter.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PrepareForShift" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SumDataAdapter" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -300,7 +330,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="PrepareForShift" xil_pn:valueState="default"/> <property xil_pn:name="Output File Name" xil_pn:value="SumDataAdapter" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -315,10 +345,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PrepareForShift_map.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SumDataAdapter_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="PrepareForShift_timesim.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SumDataAdapter_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PrepareForShift_synthesis.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SumDataAdapter_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PrepareForShift_translate.v" xil_pn:valueState="default"/> <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SumDataAdapter_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -367,8 +397,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ShiftRight" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SumDataAdapterTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ShiftRight" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -387,7 +417,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ShiftRight" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -443,7 +473,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SumDataAdapterTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

68
OperationCheckTest.vhd Normal file
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@@ -0,0 +1,68 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY OperationCheckTest IS
END OperationCheckTest;
ARCHITECTURE behavior OF OperationCheckTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT OperationCheck
PORT(
X_SIGN : IN std_logic;
Y_SIGN : IN std_logic;
OP : OUT std_logic;
RES_SIGN : OUT std_logic
);
END COMPONENT;
--Inputs
signal X_SIGN : std_logic := '0';
signal Y_SIGN : std_logic := '0';
--Outputs
signal OP : std_logic;
signal RES_SIGN : std_logic;
signal clock : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: OperationCheck PORT MAP (
X_SIGN => X_SIGN,
Y_SIGN => Y_SIGN,
OP => OP,
RES_SIGN => RES_SIGN
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
test_proc: process
begin
X_SIGN <= '0';
Y_SIGN <= '0';
wait for clock_period;
X_SIGN <= '0';
Y_SIGN <= '1';
wait for clock_period;
X_SIGN <= '1';
Y_SIGN <= '0';
wait for clock_period;
X_SIGN <= '1';
Y_SIGN <= '1';
wait for clock_period;
end process;
END;

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84
PrepareForShiftTest.vhd Normal file
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@@ -0,0 +1,84 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PrepareForShiftTest IS
END PrepareForShiftTest;
ARCHITECTURE behavior OF PrepareForShiftTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PrepareForShift
PORT(
X : IN std_logic_vector(30 downto 0);
Y : IN std_logic_vector(30 downto 0);
DIFF_EXP : OUT std_logic_vector(8 downto 0);
NEED_SWAP : OUT std_logic
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(30 downto 0) := (others => '0');
signal Y : std_logic_vector(30 downto 0) := (others => '0');
--Outputs
signal DIFF_EXP : std_logic_vector(8 downto 0);
signal NEED_SWAP : std_logic;
signal clock : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PrepareForShift PORT MAP (
X => X,
Y => Y,
DIFF_EXP => DIFF_EXP,
NEED_SWAP => NEED_SWAP
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
test_proc: process
begin
X <= "00011100" & "00001110000000000000000";
Y <= "00100011" & "00100000000000000000000";
wait for clock_period;
X <= "00110000" & "00000000111000000000000";
Y <= "10110000" & "00000001111000000000000";
wait for clock_period;
X <= "00001000" & "00000011001100000000000";
Y <= "00011000" & "00000000100000000001110";
wait for clock_period;
X <= "00001100" & "00000000000000000000000";
Y <= "00001100" & "00000000000000000000000";
wait for clock_period;
X <= "00010010" & "00000000011001000100000";
Y <= "00010010" & "00000010011000000000000";
wait for clock_period;
X <= "01011000" & "00000000100000000000000";
Y <= "01011000" & "00000000000000000000000";
wait for clock_period;
X <= "00100110" & "00000000011100001000100";
Y <= "00001010" & "00000000011100001000100";
wait for clock_period;
X <= "01111100" & "00000001110000000101010";
Y <= "00000100" & "00000101110000100110000";
wait for clock_period;
wait for clock_period;
X <= "00100000" & "00000110000000000000000";
Y <= "00001000" & "00000000100100100100000";
wait for clock_period;
end process;
END;

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6
ShiftRight.vhd
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@@ -1,7 +1,6 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
entity ShiftRight48 is entity ShiftRight48 is
port( port(
@@ -18,7 +17,9 @@ architecture ShiftRightArch of ShiftRight48 is
begin begin
asdf: process (N, PLACES) asdf: process (N, PLACES)
begin begin
case PLACES is case PLACES is
when "000000000" => RESULT <= N( 47 downto 0 ); when "000000000" => RESULT <= N( 47 downto 0 );
when "000000001" => RESULT <= "0" & N( 47 downto 1 ); when "000000001" => RESULT <= "0" & N( 47 downto 1 );
@@ -67,9 +68,10 @@ begin
when "000101100" => RESULT <= "00000000000000000000000000000000000000000000" & N( 47 downto 44 ); when "000101100" => RESULT <= "00000000000000000000000000000000000000000000" & N( 47 downto 44 );
when "000101101" => RESULT <= "000000000000000000000000000000000000000000000" & N( 47 downto 45 ); when "000101101" => RESULT <= "000000000000000000000000000000000000000000000" & N( 47 downto 45 );
when "000101110" => RESULT <= "0000000000000000000000000000000000000000000000" & N( 47 downto 46 ); when "000101110" => RESULT <= "0000000000000000000000000000000000000000000000" & N( 47 downto 46 );
when "000101111" => RESULT <= "00000000000000000000000000000000000000000000000" & N( 47 );
when others => RESULT <= "000000000000000000000000000000000000000000000000"; when others => RESULT <= "000000000000000000000000000000000000000000000000";
end case; end case;
end process; end process;
end ShiftRightArch; end ShiftRightArch;

95
ShiftRight48Test.vhd Normal file
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@@ -0,0 +1,95 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ShiftRight48Test IS
END ShiftRight48Test;
ARCHITECTURE behavior OF ShiftRight48Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ShiftRight48
PORT(
N : IN std_logic_vector(47 downto 0);
PLACES : IN std_logic_vector(8 downto 0);
RESULT : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal N : std_logic_vector(47 downto 0) := (others => '0');
signal PLACES : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal RESULT : std_logic_vector(47 downto 0);
signal clock : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ShiftRight48 PORT MAP (
N => N,
PLACES => PLACES,
RESULT => RESULT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
test_proc: process
begin
N <= "000000000011111000001110000000000000000000000000";
PLACES <= "000000000"; --0
wait for clock_period;
N <= "000000000000001010000100000000000100000000000000";
PLACES <= "000001000"; --8
wait for clock_period;
N <= "000000100000111101000000000000010000000000000000";
PLACES <= "010011100"; --156
wait for clock_period;
N <= "000011100000000001111001101000000000000111110000";
PLACES <= "000110000"; --48
wait for clock_period;
N <= "000000011111110000000001010101000110011000000000";
PLACES <= "111111111"; --511
wait for clock_period;
N <= "000000111000000000011100000000000000011100000000";
PLACES <= "000100100"; --36
wait for clock_period;
N <= "000000000000111110000000000111110000000000011111";
PLACES <= "000001101"; --13
wait for clock_period;
N <= "000001000111100000001100000000111111111111111111";
PLACES <= "000011111"; --31
wait for clock_period;
N <= "000000000011111111111111111111111000000000010001";
PLACES <= "000000111"; --7
wait for clock_period;
N <= "111111111111111111111111111111111111111111111111";
PLACES <= "001000000"; --64
wait for clock_period;
N <= "111111111111111111111111111111111111111111111111";
PLACES <= "000101111"; --47
wait for clock_period;
N <= "000000000000000000000000000000000000000000000011";
PLACES <= "000000001"; --1
wait for clock_period;
N <= "000000000000000000000011111000000000000000000000";
PLACES <= "000000000"; --0
wait for clock_period;
N <= "000000000001111000000000000000000000000000000000";
PLACES <= "000011011"; --27
wait for clock_period;
end process;
END;

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16
SpecialCasesTest.vhd
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@@ -12,8 +12,8 @@ ARCHITECTURE behavior OF SpecialCasesTest IS
PORT( PORT(
X : IN std_logic_vector(31 downto 0); X : IN std_logic_vector(31 downto 0);
Y : IN std_logic_vector(31 downto 0); Y : IN std_logic_vector(31 downto 0);
isNaN : OUT std_logic; IS_NAN : OUT std_logic;
isZero : OUT std_logic IS_ZERO : OUT std_logic
); );
END COMPONENT; END COMPONENT;
@@ -23,10 +23,8 @@ ARCHITECTURE behavior OF SpecialCasesTest IS
signal Y : std_logic_vector(31 downto 0) := (others => '0'); signal Y : std_logic_vector(31 downto 0) := (others => '0');
--Outputs --Outputs
signal isNaN : std_logic; signal IS_NAN : std_logic;
signal isZero : std_logic; signal IS_ZERO : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock : std_logic; signal clock : std_logic;
@@ -42,8 +40,8 @@ BEGIN
uut: SpecialCasesCheck PORT MAP ( uut: SpecialCasesCheck PORT MAP (
X => X, X => X,
Y => Y, Y => Y,
isNaN => isNaN, IS_NAN => IS_NAN,
isZero => isZero IS_ZERO => IS_ZERO
); );
-- Clock process definitions -- Clock process definitions
@@ -160,6 +158,6 @@ BEGIN
wait for clock_period; wait for clock_period;
end process; end process;
error <= (expectedNaN xor isNaN) or (expectedZero xor isZero); error <= (expectedNaN xor IS_NAN) or (expectedZero xor IS_ZERO);
END; END;

13
SumDataAdapter.vhd
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@@ -15,6 +15,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
signal X_FST_BIT : std_logic; signal X_FST_BIT : std_logic;
signal Y_FST_BIT : std_logic; signal Y_FST_BIT : std_logic;
signal FILL : std_logic_vector(23 downto 0);
signal N : std_logic_vector(47 downto 0);
component ShiftRight48 is component ShiftRight48 is
@@ -28,6 +30,8 @@ architecture SumDataAdapterArch of SumDataAdapter is
begin begin
FILL <= (others => '0');
X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN) X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
variable X_FST_TMP : std_logic := '0'; variable X_FST_TMP : std_logic := '0';
@@ -45,11 +49,12 @@ begin
end process; end process;
--istanziare shifter N <= Y_FST_BIT & Y_IN(22 downto 0) & FILL;
SHIFTER : ShiftRight48
port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT);
X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000"; SHIFTER : ShiftRight48
port map (N => N, PLACES => DIFF_EXP, RESULT => Y_OUT);
--X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL;
end SumDataAdapterArch; end SumDataAdapterArch;

104
SumDataAdapterTest.vhd Normal file
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@@ -0,0 +1,104 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SumDataAdapterTest IS
END SumDataAdapterTest;
ARCHITECTURE behavior OF SumDataAdapterTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SumDataAdapter
PORT(
X_IN : IN std_logic_vector(30 downto 0);
Y_IN : IN std_logic_vector(30 downto 0);
DIFF_EXP : IN std_logic_vector(8 downto 0);
X_OUT : OUT std_logic_vector(47 downto 0);
Y_OUT : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal X_IN : std_logic_vector(30 downto 0) := (others => '0');
signal Y_IN : std_logic_vector(30 downto 0) := (others => '0');
signal DIFF_EXP : std_logic_vector(8 downto 0) := (others => '0');
--Outputs
signal X_OUT : std_logic_vector(47 downto 0);
signal Y_OUT : std_logic_vector(47 downto 0);
signal clock : std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SumDataAdapter PORT MAP (
X_IN => X_IN,
Y_IN => Y_IN,
DIFF_EXP => DIFF_EXP,
X_OUT => X_OUT,
Y_OUT => Y_OUT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
test_process :process
begin
X_IN <= "111111110000010001000100000000";
Y_IN <= "001001000000000010001000000000";
DIFF_EXP <= "000000000"; --0
wait for clock_period;
X_IN <= "000000000000100000000001000000";
Y_IN <= "000000000000001111111000000000";
DIFF_EXP <= "000001000"; --8
wait for clock_period;
X_IN <= "000000000000000000111000000000";
Y_IN <= "000010000000000000000000000111";
DIFF_EXP <= "010011100"; --156
wait for clock_period;
X_IN <= "000000100000000000000000000000";
Y_IN <= "000000001000000001111111111111";
DIFF_EXP <= "000110000"; --48
wait for clock_period;
X_IN <= "000000000000000000000000010000";
Y_IN <= "000000000000000000011100000000";
DIFF_EXP <= "111111111"; --511
wait for clock_period;
X_IN <= "000000000000000000000000000000";
Y_IN <= "000000000000011100000000000000";
DIFF_EXP <= "000100100"; --36
wait for clock_period;
X_IN <= "000000000000000000000000000000";
Y_IN <= "000000000000000000000000000000";
DIFF_EXP <= "000001101"; --13
wait for clock_period;
X_IN <= "000000000000000001110001100100";
Y_IN <= "000000000000000000000011110000";
DIFF_EXP <= "000011111"; --31
wait for clock_period;
end process;
END;

57
SwapTest.vhd
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@@ -1,10 +1,6 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SwapTest IS ENTITY SwapTest IS
END SwapTest; END SwapTest;
@@ -24,16 +20,14 @@ ARCHITECTURE behavior OF SwapTest IS
--Inputs --Inputs
signal X_IN : std_logic_vector(7 downto 0) := "01010101"; signal X_IN : std_logic_vector(7 downto 0) := (others => '0');
signal Y_IN : std_logic_vector(7 downto 0) := "10101010"; signal Y_IN : std_logic_vector(7 downto 0) := (others => '0');
signal SW : std_logic := '1'; signal SW : std_logic := '0';
--Outputs --Outputs
signal X_OUT : std_logic_vector(7 downto 0); signal X_OUT : std_logic_vector(7 downto 0);
signal Y_OUT : std_logic_vector(7 downto 0); signal Y_OUT : std_logic_vector(7 downto 0);
signal clock : std_logic; signal clock : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
@@ -58,17 +52,40 @@ BEGIN
end process; end process;
-- Stimulus process test_proc: process
stim_proc: process
begin begin
-- hold reset state for 100 ns. X_IN <= "00110000";
wait for 100 ns; Y_IN <= "00010000";
SW <= '0';
wait for clock_period*10; wait for clock_period;
X_IN <= "01100000";
-- insert stimulus here Y_IN <= "01110000";
SW <= '1';
wait; wait for clock_period;
end process; X_IN <= "01101000";
Y_IN <= "00110110";
SW <= '1';
wait for clock_period;
X_IN <= "00111111";
Y_IN <= "01000000";
SW <= '0';
wait for clock_period;
X_IN <= "00101001";
Y_IN <= "00101000";
SW <= '1';
wait for clock_period;
X_IN <= "00000000";
Y_IN <= "00000000";
SW <= '1';
wait for clock_period;
X_IN <= "00110000";
Y_IN <= "00110000";
SW <= '0';
wait for clock_period;
X_IN <= "11111111";
Y_IN <= "00000000";
SW <= '1';
wait for clock_period;
end process;
END; END;

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22
TwoComplementTest.vhd
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@@ -1,10 +1,6 @@
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.ALL; USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TwoComplementTest IS ENTITY TwoComplementTest IS
END TwoComplementTest; END TwoComplementTest;
@@ -21,13 +17,11 @@ ARCHITECTURE behavior OF TwoComplementTest IS
--Inputs --Inputs
signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000"; signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := (others => '0');
--Outputs --Outputs
signal DIFF_EXP : std_logic_vector(7 downto 0); signal DIFF_EXP : std_logic_vector(7 downto 0);
signal clock : std_logic; signal clock : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns; constant clock_period : time := 10 ns;
@@ -48,20 +42,6 @@ BEGIN
wait for clock_period/2; wait for clock_period/2;
end process; end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
test_process :process test_process :process
begin begin
DIFF_EXP_C2 <= "01001110"; DIFF_EXP_C2 <= "01001110";

22
fuse.log
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@@ -1,21 +1,11 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
ISim P.20160913 (signature 0xfbc00daa) ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1 Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0 Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
Starting static elaboration Starting static elaboration
Completed static elaboration ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
Fuse Memory Usage: 95308 KB ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
Fuse CPU Usage: 2300 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
Compiling architecture behavior of entity twocomplementtest
Time Resolution for simulation is 1ps.
Compiled 5 VHDL Units
Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
Fuse Memory Usage: 103960 KB
Fuse CPU Usage: 2400 ms
GCC CPU Usage: 1480 ms

6
fuse.xmsgs
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behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="error" file="HDLCompiler" num="410" delta="unknown" >"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has <arg fmt="%d" index="1">30</arg> elements ; expected <arg fmt="%d" index="2">31</arg>
</msg>
<msg type="error" file="Simulator" num="777" delta="unknown" >Static elaboration of top level VHDL design unit <arg fmt="%s" index="1">sumdataadaptertest</arg> in library <arg fmt="%s" index="2">work</arg> failed
</msg>
</messages> </messages>

2
fuseRelaunch.cmd
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-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest" -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj" "work.SumDataAdapterTest"

16
isim.log
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ISim log file
Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0