Aggiunti test

TwoComplementTest.vhd

@@ -1,10 +1,6 @@
 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
+
 ENTITY TwoComplementTest IS
 END TwoComplementTest;
  
@@ -21,13 +17,11 @@ ARCHITECTURE behavior OF TwoComplementTest IS
     
 
    --Inputs
-   signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000";
+   signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := (others => '0');
 
  	--Outputs
    signal DIFF_EXP : std_logic_vector(7 downto 0);
 	signal clock : std_logic;
-   -- No clocks detected in port list. Replace clock below with 
-   -- appropriate port name 
  
    constant clock_period : time := 10 ns;
  
@@ -47,20 +41,6 @@ BEGIN
 		clock <= '1';
 		wait for clock_period/2;
    end process;
- 
-
-   -- Stimulus process
-   stim_proc: process
-   begin		
-      -- hold reset state for 100 ns.
-      wait for 100 ns;	
-
-      wait for clock_period*10;
-
-      -- insert stimulus here 
-
-      wait;
-   end process;
 	
 	test_process :process
    begin