40 lines
2.5 KiB
XML
40 lines
2.5 KiB
XML
<?xml version="1.0" encoding="UTF-8" ?>
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<document>
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="0" type="project"/>
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<property name="ProjectIteration" value="0" type="project"/>
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<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
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<property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
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</section>
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<section name="Project Statistics" visible="true">
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<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
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<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
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<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
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<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
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<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
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<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
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<property name="PROP_SynthTopFile" value="changed" type="process"/>
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<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
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<property name="PROP_UseSmartGuide" value="false" type="design"/>
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<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
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<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
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<property name="PROP_intWbtProjectID" value="0" type="design"/>
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<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
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<property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
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<property name="PROP_AutoTop" value="true" type="design"/>
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<property name="PROP_DevFamily" value="Spartan3" type="design"/>
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<property name="PROP_DevDevice" value="xc3s50" type="design"/>
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<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
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<property name="PROP_DevPackage" value="pq208" type="design"/>
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<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
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<property name="PROP_DevSpeed" value="-5" type="design"/>
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<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
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<property name="FILE_VHDL" value="2" type="source"/>
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</section>
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</application>
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</document>
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