34 lines
637 B
VHDL
34 lines
637 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity SpecialCasesCheck is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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isNaN, isZero: out std_logic
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);
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end SpecialCasesCheck;
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architecture SpecialCasesCheckArch of SpecialCasesCheck is
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component NaNCheck is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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isNaN: out std_logic
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);
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end component;
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component ZeroCheck is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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isZero: out std_logic
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);
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end component;
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begin
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NC: NaNCheck
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port map (X => X, Y => Y, isNaN => isNaN);
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ZC: ZeroCheck
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port map (X => X, Y => Y, isZero => isZero);
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end SpecialCasesCheckArch;
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