127 lines
4.6 KiB
Plaintext
127 lines
4.6 KiB
Plaintext
Release 14.7 - xst P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.04 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.04 secs
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-->
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Reading design: SpecialCasesCheck.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Compilation
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3) Design Hierarchy Analysis
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4) HDL Analysis
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5) HDL Synthesis
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5.1) HDL Synthesis Report
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6) Advanced HDL Synthesis
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6.1) Advanced HDL Synthesis Report
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7) Low Level Synthesis
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8) Partition Report
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9) Final Report
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9.1) Device utilization summary
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9.2) Partition Resource Summary
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9.3) TIMING REPORT
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "SpecialCasesCheck.prj"
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Input Format : mixed
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "SpecialCasesCheck"
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Output Format : NGC
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Target Device : xc3s50-5-pq208
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---- Source Options
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Top Module Name : SpecialCasesCheck
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Mux Style : Auto
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Decoder Extraction : YES
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Priority Encoder Extraction : Yes
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Shift Register Extraction : YES
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Logical Shifter Extraction : YES
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XOR Collapsing : YES
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ROM Style : Auto
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Mux Extraction : Yes
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Multiplier Style : Auto
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Automatic Register Balancing : No
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---- Target Options
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Add IO Buffers : YES
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Global Maximum Fanout : 500
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Add Generic Clock Buffer(BUFG) : 8
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Register Duplication : YES
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Slice Packing : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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Verilog 2001 : YES
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Compilation *
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=========================================================================
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Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
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Entity <typecheck> compiled.
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Entity <typecheck> (Architecture <typecheckarch>) compiled.
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ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'.
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ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'.
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ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block)
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ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist.
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-->
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Total memory usage is 584420 kilobytes
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Number of errors : 5 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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