299 lines
10 KiB
Plaintext
299 lines
10 KiB
Plaintext
Release 14.7 - xst P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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-->
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Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.05 secs
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-->
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Reading design: equalCheck.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "equalCheck.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "equalCheck"
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Output Format : NGC
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Target Device : xa6slx4-3-csg225
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---- Source Options
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Top Module Name : equalCheck
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 32
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Yes
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Use Synchronous Set : Yes
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Use Synchronous Reset : Yes
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd" into library work
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Parsing entity <equalCheck>.
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Parsing architecture <equalCheckArch> of entity <equalcheck>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity <equalCheck> (architecture <equalCheckArch>) with generics from library <work>.
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <equalCheck>.
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Related source file is "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd".
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BITCOUNT = 8
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Summary:
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Unit <equalCheck> synthesized.
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=========================================================================
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HDL Synthesis Report
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Macro Statistics
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# Xors : 1
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8-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Advanced HDL Synthesis *
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=========================================================================
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=========================================================================
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Advanced HDL Synthesis Report
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Macro Statistics
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# Xors : 1
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8-bit xor2 : 1
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=========================================================================
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=========================================================================
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* Low Level Synthesis *
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=========================================================================
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Optimizing unit <equalCheck> ...
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Mapping all equations...
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Building and optimizing final netlist ...
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Found area constraint ratio of 100 (+ 5) on block equalCheck, actual ratio is 0.
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Final Macro Processing ...
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=========================================================================
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Final Register Report
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Found no macro
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=========================================================================
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=========================================================================
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* Partition Report *
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=========================================================================
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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=========================================================================
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* Design Summary *
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=========================================================================
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Top Level Output File Name : equalCheck.ngc
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Primitive and Black Box Usage:
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------------------------------
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# BELS : 4
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# LUT5 : 1
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# LUT6 : 3
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# IO Buffers : 17
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# IBUF : 16
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# OBUF : 1
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Device utilization summary:
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---------------------------
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Selected Device : xa6slx4csg225-3
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Slice Logic Utilization:
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Number of Slice LUTs: 4 out of 2400 0%
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Number used as Logic: 4 out of 2400 0%
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Slice Logic Distribution:
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Number of LUT Flip Flop pairs used: 4
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Number with an unused Flip Flop: 4 out of 4 100%
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Number with an unused LUT: 0 out of 4 0%
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Number of fully used LUT-FF pairs: 0 out of 4 0%
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Number of unique control sets: 0
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IO Utilization:
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Number of IOs: 17
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Number of bonded IOBs: 17 out of 132 12%
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Specific Feature Utilization:
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---------------------------
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Partition Resource Summary:
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---------------------------
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No Partitions were found in this design.
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---------------------------
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=========================================================================
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Timing Report
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NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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GENERATED AFTER PLACE-and-ROUTE.
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Clock Information:
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------------------
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No clock signals found in this design
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Asynchronous Control Signals Information:
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----------------------------------------
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No asynchronous control signals found in this design
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Timing Summary:
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---------------
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Speed Grade: -3
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Minimum period: No path found
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Minimum input arrival time before clock: No path found
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Maximum output required time after clock: No path found
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Maximum combinational path delay: 7.658ns
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Timing Details:
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---------------
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All values displayed in nanoseconds (ns)
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=========================================================================
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Timing constraint: Default path analysis
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Total number of paths / destination ports: 20 / 1
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-------------------------------------------------------------------------
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Delay: 7.658ns (Levels of Logic = 5)
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Source: X<7> (PAD)
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Destination: isEqual (PAD)
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Data Path: X<7> to isEqual
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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IBUF:I->O 1 1.222 0.944 X_7_IBUF (X_7_IBUF)
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LUT6:I0->O 1 0.203 0.924 isEqual<0>4 (isEqual<0>3)
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LUT5:I0->O 1 0.203 0.808 isEqual<0>5_SW0 (N2)
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LUT6:I3->O 1 0.205 0.579 isEqual<0>5 (isEqual_OBUF)
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OBUF:I->O 2.571 isEqual_OBUF (isEqual)
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----------------------------------------
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Total 7.658ns (4.404ns logic, 3.254ns route)
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(57.5% logic, 42.5% route)
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=========================================================================
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Cross Clock Domains Report:
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--------------------------
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=========================================================================
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Total REAL time to Xst completion: 3.00 secs
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Total CPU time to Xst completion: 3.71 secs
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-->
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Total memory usage is 474280 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 0 ( 0 filtered)
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