81 lines
1.6 KiB
VHDL
81 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity PipelineStageTwo is
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port(
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A, B : in std_logic_vector(31 downto 0);
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DIFF_EXP_ABS : in std_logic_vector(8 downto 0);
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IS_NAN_IN, IS_ZERO_IN : in std_logic;
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EXP : out std_logic_vector(7 downto 0);
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SUM_RESULT : out std_logic_vector(47 downto 0);
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SUM_OF : out std_logic;
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RES_SIGN : out std_logic;
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IS_NAN_OUT, IS_ZERO_OUT : out std_logic
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);
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end PipelineStageTwo;
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architecture StageTwoArch of PipelineStageTwo is
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component SumDataAdapter is
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port(
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X_IN, Y_IN : in std_logic_vector(30 downto 0);
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DIFF_EXP : in std_logic_vector(8 downto 0);
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X_OUT, Y_OUT : out std_logic_vector(47 downto 0)
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);
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end component;
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component CarryLookAhead is
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port(
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X, Y : in std_logic_vector(47 downto 0);
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OP : in std_logic;
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RESULT : out std_logic_vector(47 downto 0);
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OVERFLOW : out std_logic
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);
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end component;
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component OperationCheck is
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port(
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X_SIGN, Y_SIGN : in std_logic;
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OP, RES_SIGN : out std_logic
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);
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end component;
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signal MANT_EXT_A : std_logic_vector(47 downto 0);
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signal MANT_EXT_B : std_logic_vector(47 downto 0);
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signal OP : std_logic;
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begin
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SH : SumDataAdapter
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port map (
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X_IN => A(30 downto 0), Y_IN => B(30 downto 0),
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DIFF_EXP => DIFF_EXP_ABS, X_OUT => MANT_EXT_A, Y_OUT => MANT_EXT_B
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);
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OC : OperationCheck
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port map (X_SIGN => A(31), Y_SIGN => B(31), OP => OP, RES_SIGN => RES_SIGN);
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CLA : CarryLookAhead
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port map (
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X => MANT_EXT_A,
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Y => MANT_EXT_B,
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OP => OP,
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RESULT => SUM_RESULT,
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OVERFLOW => SUM_OF
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);
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IS_NAN_OUT <= IS_NAN_IN;
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IS_ZERO_OUT <= IS_ZERO_IN;
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EXP <= A(30 downto 23);
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end StageTwoArch;
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