105 lines
2.7 KiB
VHDL
105 lines
2.7 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY SumDataAdapterTest IS
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END SumDataAdapterTest;
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ARCHITECTURE behavior OF SumDataAdapterTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT SumDataAdapter
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PORT(
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X_IN : IN std_logic_vector(30 downto 0);
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Y_IN : IN std_logic_vector(30 downto 0);
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DIFF_EXP : IN std_logic_vector(8 downto 0);
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X_OUT : OUT std_logic_vector(47 downto 0);
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Y_OUT : OUT std_logic_vector(47 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal X_IN : std_logic_vector(30 downto 0) := (others => '0');
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signal Y_IN : std_logic_vector(30 downto 0) := (others => '0');
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signal DIFF_EXP : std_logic_vector(8 downto 0) := (others => '0');
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--Outputs
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signal X_OUT : std_logic_vector(47 downto 0);
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signal Y_OUT : std_logic_vector(47 downto 0);
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: SumDataAdapter PORT MAP (
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X_IN => X_IN,
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Y_IN => Y_IN,
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DIFF_EXP => DIFF_EXP,
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X_OUT => X_OUT,
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Y_OUT => Y_OUT
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clock_period*10;
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-- insert stimulus here
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wait;
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end process;
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test_process :process
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begin
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X_IN <= "111111110000010001000100000000";
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Y_IN <= "001001000000000010001000000000";
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DIFF_EXP <= "000000000"; --0
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wait for clock_period;
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X_IN <= "000000000000100000000001000000";
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Y_IN <= "000000000000001111111000000000";
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DIFF_EXP <= "000001000"; --8
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wait for clock_period;
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X_IN <= "000000000000000000111000000000";
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Y_IN <= "000010000000000000000000000111";
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DIFF_EXP <= "010011100"; --156
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wait for clock_period;
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X_IN <= "000000100000000000000000000000";
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Y_IN <= "000000001000000001111111111111";
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DIFF_EXP <= "000110000"; --48
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wait for clock_period;
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X_IN <= "000000000000000000000000010000";
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Y_IN <= "000000000000000000011100000000";
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DIFF_EXP <= "111111111"; --511
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wait for clock_period;
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X_IN <= "000000000000000000000000000000";
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Y_IN <= "000000000000011100000000000000";
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DIFF_EXP <= "000100100"; --36
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wait for clock_period;
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X_IN <= "000000000000000000000000000000";
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Y_IN <= "000000000000000000000000000000";
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DIFF_EXP <= "000001101"; --13
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wait for clock_period;
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X_IN <= "000000000000000001110001100100";
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Y_IN <= "000000000000000000000011110000";
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DIFF_EXP <= "000011111"; --31
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wait for clock_period;
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end process;
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END;
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