23 lines
356 B
VHDL
23 lines
356 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Normalizer is
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port(
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SIGN : in std_logic;
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EXP : in std_logic_vector(7 downto 0);
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MANT : in std_logic_vector(47 downto 0);
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OVERFLOW : in std_logic;
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IEEE_754_SUM : out std_logic_vector(31 downto 0)
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);
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end Normalizer;
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architecture NormalizerArch of Normalizer is
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begin
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end NormalizerArch;
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