92 lines
1.9 KiB
VHDL
92 lines
1.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY SwapTest IS
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END SwapTest;
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ARCHITECTURE behavior OF SwapTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Swap
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PORT(
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X_IN : IN std_logic_vector(7 downto 0);
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Y_IN : IN std_logic_vector(7 downto 0);
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SW : IN std_logic;
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X_OUT : OUT std_logic_vector(7 downto 0);
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Y_OUT : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal X_IN : std_logic_vector(7 downto 0) := (others => '0');
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signal Y_IN : std_logic_vector(7 downto 0) := (others => '0');
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signal SW : std_logic := '0';
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--Outputs
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signal X_OUT : std_logic_vector(7 downto 0);
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signal Y_OUT : std_logic_vector(7 downto 0);
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Swap PORT MAP (
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X_IN => X_IN,
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Y_IN => Y_IN,
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SW => SW,
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X_OUT => X_OUT,
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Y_OUT => Y_OUT
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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X_IN <= "00110000";
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Y_IN <= "00010000";
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SW <= '0';
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wait for clock_period;
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X_IN <= "01100000";
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Y_IN <= "01110000";
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SW <= '1';
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wait for clock_period;
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X_IN <= "01101000";
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Y_IN <= "00110110";
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SW <= '1';
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wait for clock_period;
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X_IN <= "00111111";
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Y_IN <= "01000000";
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SW <= '0';
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wait for clock_period;
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X_IN <= "00101001";
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Y_IN <= "00101000";
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SW <= '1';
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wait for clock_period;
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X_IN <= "00000000";
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Y_IN <= "00000000";
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SW <= '1';
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wait for clock_period;
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X_IN <= "00110000";
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Y_IN <= "00110000";
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SW <= '0';
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wait for clock_period;
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X_IN <= "11111111";
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Y_IN <= "00000000";
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SW <= '1';
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wait for clock_period;
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end process;
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END;
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