102 lines
2.5 KiB
VHDL
102 lines
2.5 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 08:37:57 08/27/2019
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-- Design Name:
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-- Module Name: /home/ise/gianni/IEEE754Adder/tb.vhd
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-- Project Name: IEEE754Adder
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: pr
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY tb IS
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END tb;
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ARCHITECTURE behavior OF tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT pr
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PORT(
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xExp : IN std_logic_vector(7 downto 0);
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yExp : IN std_logic_vector(7 downto 0);
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xOut : OUT std_logic_vector(7 downto 0);
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yOut : OUT std_logic_vector(7 downto 0);
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needSwap : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal xExp : std_logic_vector(7 downto 0) := "01010101";
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signal yExp : std_logic_vector(7 downto 0) := "01010001";
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--Outputs
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signal xOut : std_logic_vector(7 downto 0);
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signal yOut : std_logic_vector(7 downto 0);
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signal needSwap : std_logic;
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signal clock: std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: pr PORT MAP (
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xExp => xExp,
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yExp => yExp,
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xOut => xOut,
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yOut => yOut,
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needSwap => needSwap
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clock_period*10;
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-- insert stimulus here
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wait;
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end process;
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END;
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