| Project Statistics |
| PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
| PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
| PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
| PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
| PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
| PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds |
PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2019-08-17T16:51:15 |
PROP_intWbtProjectID=4B48FA10A560F77F46DA66FD7F346092 |
| PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
| PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
| PROP_xilxSynthAddBufg_spartan6=32 |
PROP_xstUseClockEnable_spartan6=Yes |
| PROP_xstUseSyncReset_spartan6=Yes |
PROP_xstUseSyncSet_spartan6=Yes |
| PROPEXT_mapTimingMode_spartan6=Non Timing Driven |
PROP_AutoTop=false |
| PROP_DevFamily=Automotive Spartan6 |
PROP_DevDevice=xa6slx4 |
| PROP_DevFamilyPMName=aspartan6 |
PROP_DevPackage=csg225 |
| PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
| PROP_PreferredLanguage=VHDL |
FILE_VHDL=5 |