Release 14.7 Map P.20131013 (lin64) Xilinx Map Application Log File for Design 'SpecialCasesCheck' Design Information ------------------ Command Line : map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf Target Device : xa6slx4 Target Package : csg225 Target Speed : -3 Mapper Version : aspartan6 -- $Revision: 1.55 $ Mapped Date : Sat Aug 24 12:14:20 2019 Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 3 secs Total CPU time at the beginning of Placer: 3 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:1afc) REAL time: 3 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:1afc) REAL time: 3 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:1afc) REAL time: 3 secs Phase 4.2 Initial Placement for Architecture Specific Features ... .... Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:1afc) REAL time: 4 secs Phase 5.36 Local Placement Optimization Phase 5.36 Local Placement Optimization (Checksum:1afc) REAL time: 4 secs Phase 6.30 Global Clock Region Assignment Phase 6.30 Global Clock Region Assignment (Checksum:1afc) REAL time: 4 secs Phase 7.3 Local Placement Optimization ... .... Phase 7.3 Local Placement Optimization (Checksum:789e990e) REAL time: 4 secs Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization (Checksum:789e990e) REAL time: 4 secs Phase 9.8 Global Placement ................... ......................... Phase 9.8 Global Placement (Checksum:97cecb7e) REAL time: 4 secs Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization (Checksum:97cecb7e) REAL time: 4 secs Phase 11.18 Placement Optimization Phase 11.18 Placement Optimization (Checksum:bebeaa60) REAL time: 4 secs Phase 12.5 Local Placement Optimization Phase 12.5 Local Placement Optimization (Checksum:bebeaa60) REAL time: 4 secs Phase 13.34 Placement Validation Phase 13.34 Placement Validation (Checksum:bebeaa60) REAL time: 4 secs Total REAL time to Placer completion: 4 secs Total CPU time to Placer completion: 4 secs Running post-placement packing... Writing output files... Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice Registers: 0 out of 4,800 0% Number of Slice LUTs: 26 out of 2,400 1% Number used as logic: 26 out of 2,400 1% Number using O6 output only: 25 Number using O5 output only: 0 Number using O5 and O6: 1 Number used as ROM: 0 Number used as Memory: 0 out of 1,200 0% Slice Logic Distribution: Number of occupied Slices: 10 out of 600 1% Number of MUXCYs used: 12 out of 1,200 1% Number of LUT Flip Flop pairs used: 26 Number with an unused Flip Flop: 26 out of 26 100% Number with an unused LUT: 0 out of 26 0% Number of fully used LUT-FF pairs: 0 out of 26 0% Number of slice register sites lost to control set restrictions: 0 out of 4,800 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 66 out of 132 50% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 12 0% Number of RAMB8BWERs: 0 out of 24 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 0 out of 16 0% Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 200 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% Number of OLOGIC2/OSERDES2s: 0 out of 200 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 8 0% Number of ICAPs: 0 out of 1 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 1.78 Peak Memory Usage: 734 MB Total REAL time to MAP completion: 5 secs Total CPU time to MAP completion: 5 secs Mapping completed. See MAP report file "SpecialCasesCheck_map.mrp" for details.