| SpecialCasesCheck Project Status (08/24/2019 - 12:14:34) | |||
| Project File: | IEEE754Adder.xise | Parser Errors: | No Errors |
| Module Name: | SpecialCasesCheck | Implementation State: | Placed and Routed |
| Target Device: | xa6slx4-3csg225 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
1 Warning (0 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Registers | 0 | 4,800 | 0% | ||
| Number of Slice LUTs | 26 | 2,400 | 1% | ||
| Number used as logic | 26 | 2,400 | 1% | ||
| Number using O6 output only | 25 | ||||
| Number using O5 output only | 0 | ||||
| Number using O5 and O6 | 1 | ||||
| Number used as ROM | 0 | ||||
| Number used as Memory | 0 | 1,200 | 0% | ||
| Number of occupied Slices | 10 | 600 | 1% | ||
| Number of MUXCYs used | 12 | 1,200 | 1% | ||
| Number of LUT Flip Flop pairs used | 26 | ||||
| Number with an unused Flip Flop | 26 | 26 | 100% | ||
| Number with an unused LUT | 0 | 26 | 0% | ||
| Number of fully used LUT-FF pairs | 0 | 26 | 0% | ||
| Number of slice register sites lost to control set restrictions |
0 | 4,800 | 0% | ||
| Number of bonded IOBs | 66 | 132 | 50% | ||
| Number of RAMB16BWERs | 0 | 12 | 0% | ||
| Number of RAMB8BWERs | 0 | 24 | 0% | ||
| Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% | ||
| Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
| Number of BUFG/BUFGMUXs | 0 | 16 | 0% | ||
| Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
| Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% | ||
| Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% | ||
| Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% | ||
| Number of BSCANs | 0 | 4 | 0% | ||
| Number of BUFHs | 0 | 128 | 0% | ||
| Number of BUFPLLs | 0 | 8 | 0% | ||
| Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
| Number of DSP48A1s | 0 | 8 | 0% | ||
| Number of ICAPs | 0 | 1 | 0% | ||
| Number of PCILOGICSEs | 0 | 2 | 0% | ||
| Number of PLL_ADVs | 0 | 2 | 0% | ||
| Number of PMVs | 0 | 1 | 0% | ||
| Number of STARTUPs | 0 | 1 | 0% | ||
| Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
| Average Fanout of Non-Clock Nets | 1.78 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Sat Aug 24 12:14:14 2019 | 0 | 1 Warning (0 new) | 0 | |
| Translation Report | Current | Sat Aug 24 12:14:17 2019 | 0 | 0 | 0 | |
| Map Report | Current | Sat Aug 24 12:14:25 2019 | 0 | 0 | 5 Infos (0 new) | |
| Place and Route Report | Current | Sat Aug 24 12:14:30 2019 | 0 | 0 | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Sat Aug 24 12:14:33 2019 | 0 | 0 | 4 Infos (0 new) | |
| Bitgen Report | Out of Date | Sat Aug 24 10:52:30 2019 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Sat Aug 24 12:12:57 2019 | |
| Post-Synthesis Simulation Model Report | Out of Date | Sat Aug 24 10:53:07 2019 | |
| WebTalk Report | Out of Date | Sat Aug 24 10:52:31 2019 | |
| WebTalk Log File | Out of Date | Sat Aug 24 10:52:32 2019 | |