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Creato modulo CarryLookAhead

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This commit is contained in:
Giulio
2019-08-29 18:08:25 +02:00
parent f4f0989ac4
commit f8ee1d5e27
13 changed files with 224 additions and 117 deletions
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42
AddSub.vhd
View File

@@ -2,41 +2,57 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AddSub is
generic( BITCOUNT: integer := 8 );
generic(
BITCOUNT : integer := 8
);
port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
isSub: in std_logic := '0';
result: out std_logic_vector((BITCOUNT-1) downto 0);
overflow: out std_logic
IS_SUB : in std_logic := '0';
RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
OVERFLOW : out std_logic
);
end AddSub;
architecture AddSubArch of AddSub is
component Adder is
generic( BITCOUNT: integer := 8 );
generic(
BITCOUNT : integer := 8
);
port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
carry_in: in std_logic;
result: out std_logic_vector((BITCOUNT-1) downto 0);
carry_out: out std_logic
CARRY_IN : in std_logic;
RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
CARRY_OUT : out std_logic
);
end component;
signal Y2 : std_logic_vector((BITCOUNT-1) downto 0);
signal C_out: std_logic;
signal C_OUT : std_logic;
begin
y2proc: process(Y, isSub)
Y2_PROCESS : process(Y, IS_SUB)
begin
for i in Y2'range loop
Y2(i) <= Y(i) xor isSub;
Y2(i) <= Y(i) xor IS_SUB;
end loop;
end process;
ADD : Adder
generic map (BITCOUNT => BITCOUNT)
port map ( X => X, Y => Y2, carry_in => isSub, result => result, carry_out => C_out );
port map (X => X, Y => Y2, CARRY_IN => IS_SUB, RESULT => RESULT, CARRY_OUT => C_OUT);
OVERFLOW <= ((not IS_SUB) and C_OUT) or (IS_SUB and (not C_OUT));
overflow <= ((not isSub) and C_out) or (isSub and (not C_out));
end AddSubArch;

54
Adder.vhd
View File

@@ -3,37 +3,51 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
generic( BITCOUNT: integer := 8 );
generic(
BITCOUNT : integer := 8
);
port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
carry_in: in std_logic;
result: out std_logic_vector((BITCOUNT-1) downto 0);
carry_out: out std_logic
CARRY_IN : in std_logic;
RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
CARRY_OUT : out std_logic
);
end Adder;
architecture CarryLookAheadArch of Adder is
signal generation: std_logic_vector((BITCOUNT-1) downto 0);
signal propagation: std_logic_vector((BITCOUNT-1) downto 0);
signal carry: std_logic_vector((BITCOUNT-1) downto 0);
signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0);
begin
generation <= X and Y;
propagation <= X or Y;
sum_no_carry <= X xor Y;
carry_look_ahead: process (generation, propagation, carry_in)
variable C: std_logic;
signal GENERATION : std_logic_vector((BITCOUNT-1) downto 0);
signal PROPAGATION : std_logic_vector((BITCOUNT-1) downto 0);
signal CARRY : std_logic_vector((BITCOUNT-1) downto 0);
signal SUM_NO_CARRY : std_logic_vector((BITCOUNT-1) downto 0);
begin
C := carry_in;
carry(0) <= C;
GENERATION <= X and Y;
PROPAGATION <= X or Y;
SUM_NO_CARRY <= X xor Y;
CARRY_LOOK_AHEAD_PROCESS : process (GENERATION, PROPAGATION, CARRY_IN)
variable C : std_logic;
begin
C := CARRY_IN;
CARRY(0) <= C;
for i in 1 to (BITCOUNT-1) loop
C := generation(i-1) or (propagation(i-1) and C);
carry(i) <= C;
C := GENERATION(i-1) or (PROPAGATION(i-1) and C);
CARRY(i) <= C;
end loop;
end process;
result <= sum_no_carry xor carry;
carry_out <= (X(BITCOUNT-1) and Y(BITCOUNT-1)) or (X(BITCOUNT-1) and carry(BITCOUNT-1)) or (carry(BITCOUNT-1) and Y(BITCOUNT-1));
RESULT <= SUM_NO_CARRY xor CARRY;
CARRY_OUT <= (X(BITCOUNT-1) and Y(BITCOUNT-1)) or (X(BITCOUNT-1) and CARRY(BITCOUNT-1)) or (CARRY(BITCOUNT-1) and Y(BITCOUNT-1));
end CarryLookAheadArch;

43
CarryLookAhead.vhd Normal file
View File

@@ -0,0 +1,43 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CarryLookAhead is
port(
X, Y : in std_logic_vector(47 downto 0);
OP : in std_logic;
RESULT : out std_logic_vector(47 downto 0);
OVERFLOW : out std_logic
);
end CarryLookAhead;
architecture CarryLookAheadArch of CarryLookAhead is
--signal OVERFLOW_TMP : std_logic;
component AddSub is
generic(
BITCOUNT : integer := 8
);
port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
IS_SUB : in std_logic := '0';
RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
OVERFLOW : out std_logic
);
end component;
begin
CLA : AddSub
generic map (BITCOUNT => 48)
port map (X => X, Y => Y, IS_SUB => OP, RESULT => RESULT, OVERFLOW => OVERFLOW);
--OVERFLOW <= OVERFLOW_TMP xor OP;
end CarryLookAheadArch;

6
Comparator.vhd
View File

@@ -4,7 +4,9 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is
generic( BITCOUNT : integer := 8 );
generic(
BITCOUNT : integer := 8
);
port(
X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
@@ -23,7 +25,7 @@ begin
X_GT_Y <= X_MANT and (not Y_MANT);
Y_GT_X <= (not X_MANT) and Y_MANT;
NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
NEED_SWAP_PROCESS : process (X_GT_Y, Y_GT_X)
variable SWAP : std_logic;
variable SWAP_CARRY : std_logic;

10
EqualCheck.vhd
View File

@@ -1,8 +1,6 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_1164.ALL;
entity EqualCheck is
generic(
@@ -13,19 +11,12 @@ entity EqualCheck is
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
IS_EQUAL : out std_logic
);
end EqualCheck;
architecture EqualCheckArch of EqualCheck is
end EqualCheck;
signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
begin
@@ -37,6 +28,5 @@ begin
begin
RES_COMPUTE: process (COMP_VEC)
RES_TMP := '0';

34
IEEE754Adder.xise
View File

@@ -93,6 +93,10 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="179"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="244"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
</files>
<properties>
@@ -148,8 +152,8 @@
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -213,9 +217,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|AddSub|AddSubArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="AddSub.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/AddSub" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CarryLookAhead|CarryLookAheadArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="CarryLookAhead.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CarryLookAhead" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -284,11 +288,11 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="AddSub" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="CarryLookAhead" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -299,10 +303,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="AddSub_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="AddSub_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="AddSub_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="AddSub_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CarryLookAhead_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CarryLookAhead_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CarryLookAhead_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CarryLookAhead_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -327,7 +331,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="AddSub" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="CarryLookAhead" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -351,8 +355,6 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddSubTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddSubTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TwoComplementTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
@@ -373,7 +375,6 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddSubTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -430,10 +431,9 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddSubTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>

3
OperationCheck.vhd
View File

@@ -2,15 +2,18 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OperationCheck is
port(
X_SIGN, Y_SIGN : in std_logic;
OP, RES_SIGN : out std_logic
);
end OperationCheck;
architecture OperationCheckArch of OperationCheck is
begin
OP <= X_SIGN xor Y_SIGN;
RES_SIGN <= X_SIGN;

65
PrepareForShift.vhd
View File

@@ -2,41 +2,80 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PrepareForShift is
port(
X, Y: in std_logic_vector(31 downto 0);
X, Y : in std_logic_vector(30 downto 0);
DIFF_EXP : out std_logic_vector(8 downto 0);
SW: out std_logic
NEED_SWAP : out std_logic
);
end PrepareForShift;
architecture PrepareForShiftArch of PrepareForShift is
signal LT : std_logic;
signal EQ : std_logic;
signal RESULT : std_logic_vector(7 downto 0);
signal OVERFLOW : std_logic;
component Comparator is
generic( BITCOUNT: integer := 8 );
port(
xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic
generic(
BITCOUNT: integer := 8
);
port(
X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
NEED_SWAP : out std_logic
);
end component;
component AddSub is
generic(
BITCOUNT : integer := 8
);
port(
X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
IS_SUB : in std_logic := '0';
RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
OVERFLOW : out std_logic
);
end component;
begin
C : Comparator
port map (xT => X(22 downto 0), yT => Y(22 downto 0), needSwap => LT);
generic map (BITCOUNT => 23)
port map (X_MANT => X(22 downto 0), Y_MANT => Y(22 downto 0), NEED_SWAP => LT);
--istaziare sommatore la cui uscita va mappata in X(31 downto 23), Y(31 downto 23), DIFF_EXP
ADD_SUB : AddSub
generic map (BITCOUNT => 8)
port map (X => X(30 downto 23), Y => Y(30 downto 23), IS_SUB => '1', RESULT => RESULT, OVERFLOW => OVERFLOW);
EQ <= '0';
EQUAL_EXP_PROCESS : process (RESULT, OVERFLOW)
variable EQ_TMP : std_logic;
O: process (DIFF_EXP)
begin
for i in 8 downto 0 loop
EQ <= EQ or DIFF_EXP(i);
EQ_TMP := '0';
for i in 7 downto 0 loop
EQ_TMP := EQ_TMP or RESULT(i);
end loop;
EQ_TMP := EQ_TMP or OVERFLOW;
EQ_TMP := not EQ_TMP;
EQ <= EQ_TMP;
end process;
SW <= DIFF_EXP(8) or (EQ and LT);
NEED_SWAP <= OVERFLOW or (EQ and LT);
DIFF_EXP <= OVERFLOW & RESULT;
end PrepareForShiftArch;

4
TypeCheck.vhd
View File

@@ -22,7 +22,7 @@ begin
G_BUS <= N(30 downto 23);
T_BUS <= N(22 downto 0);
G_compute: process (G_BUS)
G_PROCESS : process (G_BUS)
variable G_TMP : std_logic;
@@ -38,7 +38,7 @@ begin
end process;
T_compute: process (T_BUS)
T_PROCESS : process (T_BUS)
variable T_TMP : std_logic;

2
ZeroCheck.vhd
View File

@@ -42,7 +42,7 @@ begin
IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
AbsCheck: EqualCheck
ABS_CHECK : EqualCheck
generic map ( BITCOUNT => 31 )
port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);