Merge branch 'master' of https://github.com/optimize-fast/IEEE754Adder
This commit is contained in:
20
AddSub.vhd
Normal file
20
AddSub.vhd
Normal file
@@ -0,0 +1,20 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
|
||||
entity AddSub is
|
||||
generic( BITCOUNT: integer := 8 );
|
||||
port(
|
||||
X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
|
||||
isSub: in std_logic := 0;
|
||||
result: out std_logic_vector((BITCOUNT-1) downto 0)
|
||||
);
|
||||
end AddSub;
|
||||
|
||||
architecture CLAAddSubArch of AddSub is
|
||||
|
||||
begin
|
||||
|
||||
|
||||
end CLAAddSubArch;
|
||||
|
||||
36
Adder.vhd
36
Adder.vhd
@@ -0,0 +1,36 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
|
||||
entity Adder is
|
||||
generic( BITCOUNT: integer := 8 );
|
||||
port(
|
||||
X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
|
||||
carry_in: in std_logic;
|
||||
result: out std_logic_vector((BITCOUNT-1) downto 0);
|
||||
carry_out: out std_logic
|
||||
);
|
||||
end Adder;
|
||||
|
||||
architecture CarryLookAheadArch of Adder is
|
||||
signal generation: std_logic_vector((BITCOUNT-1) downto 0);
|
||||
signal propagation: std_logic_vector((BITCOUNT-1) downto 0);
|
||||
signal carry: std_logic_vector((BITCOUNT-1) downto 0);
|
||||
signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0);
|
||||
begin
|
||||
generation <= X and Y;
|
||||
propagation <= X or Y;
|
||||
sum_no_carry <= X xor Y;
|
||||
|
||||
carry_look_ahead: process (generation, propagation, carry, carry_in)
|
||||
begin
|
||||
carry(0) <= carry_in;
|
||||
for i in (BITCOUNT-1) downto 1 loop
|
||||
carry(i) <= generation(i) or (propagation(i) and carry(i-1));
|
||||
end loop;
|
||||
end process;
|
||||
|
||||
result <= sum_no_carry xor carry;
|
||||
carry_out <= sum_no_carry(BITCOUNT-1) xor carry(BITCOUNT-1);
|
||||
end CarryLookAheadArch;
|
||||
|
||||
|
||||
90
AdderTest.vhd
Normal file
90
AdderTest.vhd
Normal file
@@ -0,0 +1,90 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:01:26 08/24/2019
|
||||
-- Design Name:
|
||||
-- Module Name: /home/Luca/ISE/IEEE754Adder/AdderTest.vhd
|
||||
-- Project Name: IEEE754Adder
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: Adder
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY AdderTest IS
|
||||
END AdderTest;
|
||||
|
||||
ARCHITECTURE behavior OF AdderTest IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT Adder
|
||||
PORT(
|
||||
X : IN std_logic_vector(7 downto 0);
|
||||
Y : IN std_logic_vector(7 downto 0);
|
||||
carry_in : IN std_logic;
|
||||
result : OUT std_logic_vector(7 downto 0);
|
||||
carry_out : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal X : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal Y : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal carry_in : std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal result : std_logic_vector(7 downto 0);
|
||||
signal carry_out : std_logic;
|
||||
-- No clocks detected in port list. Replace clock below with
|
||||
-- appropriate port name
|
||||
signal clock: std_logic;
|
||||
|
||||
constant clock_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: Adder PORT MAP (
|
||||
X => X,
|
||||
Y => Y,
|
||||
carry_in => carry_in,
|
||||
result => result,
|
||||
carry_out => carry_out
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clock_process :process
|
||||
begin
|
||||
clock <= '0';
|
||||
wait for clock_period/2;
|
||||
clock <= '1';
|
||||
wait for clock_period/2;
|
||||
end process;
|
||||
|
||||
x <= "00010101";
|
||||
y <= "00001110";
|
||||
|
||||
END;
|
||||
BIN
AdderTest_isim_beh.exe
Executable file
BIN
AdderTest_isim_beh.exe
Executable file
Binary file not shown.
BIN
AdderTest_isim_beh.wdb
Normal file
BIN
AdderTest_isim_beh.wdb
Normal file
Binary file not shown.
@@ -1,449 +1,906 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
|
||||
|
||||
<header>
|
||||
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- This file contains project source information including a list of -->
|
||||
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
</header>
|
||||
|
||||
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
|
||||
|
||||
<files>
|
||||
|
||||
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
|
||||
</file>
|
||||
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
|
||||
</file>
|
||||
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="160"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="160"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
|
||||
</file>
|
||||
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
|
||||
</file>
|
||||
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
|
||||
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
|
||||
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
</file>
|
||||
<file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
|
||||
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
|
||||
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
|
||||
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="160"/>
|
||||
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="160"/>
|
||||
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
||||
</file>
|
||||
|
||||
<file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/>
|
||||
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/>
|
||||
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
|
||||
|
||||
</file>
|
||||
|
||||
</files>
|
||||
|
||||
|
||||
|
||||
<properties>
|
||||
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TwoComplement|TwoComplementArch" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="TwoComplement.vhd" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/TwoComplement" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SpecialCasesCheck|SpecialCasesCheckArch" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="SpecialCasesCheck.vhd" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SpecialCasesCheck" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TwoComplement_map.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="TwoComplement_timesim.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TwoComplement_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TwoComplement_translate.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SpecialCasesCheck_map.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TwoComplementTest" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="SpecialCasesCheck.ucf" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-17T16:51:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4B48FA10A560F77F46DA66FD7F346092" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-24T16:50:37" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="444E2DA6F875B400D5DCC2E6514F4196" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
|
||||
</properties>
|
||||
|
||||
|
||||
|
||||
<bindings/>
|
||||
|
||||
|
||||
|
||||
<libraries/>
|
||||
|
||||
|
||||
|
||||
<autoManagedFiles>
|
||||
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
|
||||
<!-- include files. -->
|
||||
|
||||
</autoManagedFiles>
|
||||
|
||||
|
||||
|
||||
</project>
|
||||
|
||||
|
||||
492
IEEE754Adder.xise~
Normal file
492
IEEE754Adder.xise~
Normal file
@@ -0,0 +1,492 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<<<<<<< HEAD
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
=======
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
</file>
|
||||
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
|
||||
</file>
|
||||
<<<<<<< HEAD
|
||||
<file xil_pn:name="SpecialCasesCheck.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
|
||||
=======
|
||||
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
|
||||
</file>
|
||||
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="160"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="160"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
|
||||
</file>
|
||||
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="FullAdder.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FullAdder|FullAdderArch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="FullAdder.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FullAdder" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="FullAdder" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="FullAdder_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="FullAdder_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FullAdder_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FullAdder_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="FullAdder" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/FullAdderTest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="SpecialCasesCheck.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<<<<<<< HEAD
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AdderTest|behavior" xil_pn:valueState="non-default"/>
|
||||
=======
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|FullAdderTest|behavior" xil_pn:valueState="non-default"/>
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-24T16:50:37" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="444E2DA6F875B400D5DCC2E6514F4196" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/Adder" xil_pn:name="SpecialCasesCheck.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
BIN
SpecialCasesCheck.xdl
Normal file
BIN
SpecialCasesCheck.xdl
Normal file
Binary file not shown.
BIN
SpecialCasesCheck_isim_beh.exe
Executable file
BIN
SpecialCasesCheck_isim_beh.exe
Executable file
Binary file not shown.
@@ -18,6 +18,8 @@ architecture EqualCheckArch of EqualCheck is
|
||||
|
||||
signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
|
||||
|
||||
|
||||
|
||||
begin
|
||||
|
||||
COMP_VEC <= X xor Y;
|
||||
|
||||
46
fuse.log~
Normal file
46
fuse.log~
Normal file
@@ -0,0 +1,46 @@
|
||||
<<<<<<< HEAD
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
|
||||
ISim P.20131013 (signature 0xfbc00daa)
|
||||
Number of CPUs detected in this system: 4
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 8
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
|
||||
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 94252 KB
|
||||
Fuse CPU Usage: 950 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
|
||||
Compiling architecture behavior of entity addertest
|
||||
Time Resolution for simulation is 1ps.
|
||||
Waiting for 1 sub-compilation(s) to finish...
|
||||
Compiled 5 VHDL Units
|
||||
Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
|
||||
Fuse Memory Usage: 657936 KB
|
||||
Fuse CPU Usage: 980 ms
|
||||
GCC CPU Usage: 140 ms
|
||||
=======
|
||||
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
Number of CPUs detected in this system: 1
|
||||
Turning on mult-threading, number of parallel sub-compilation jobs: 0
|
||||
Determining compilation order of HDL files
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work
|
||||
Starting static elaboration
|
||||
Completed static elaboration
|
||||
Fuse Memory Usage: 95308 KB
|
||||
Fuse CPU Usage: 2530 ms
|
||||
Compiling package standard
|
||||
Compiling package std_logic_1164
|
||||
Compiling architecture fulladderarch of entity FullAdder [fulladder_default]
|
||||
Compiling architecture behavior of entity fulladdertest
|
||||
Time Resolution for simulation is 1ps.
|
||||
Compiled 5 VHDL Units
|
||||
Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe
|
||||
Fuse Memory Usage: 103940 KB
|
||||
Fuse CPU Usage: 2640 ms
|
||||
GCC CPU Usage: 440 ms
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
5
fuseRelaunch.cmd~
Normal file
5
fuseRelaunch.cmd~
Normal file
@@ -0,0 +1,5 @@
|
||||
<<<<<<< HEAD
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj" "work.AdderTest"
|
||||
=======
|
||||
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
35
isim.log~
Normal file
35
isim.log~
Normal file
@@ -0,0 +1,35 @@
|
||||
ISim log file
|
||||
<<<<<<< HEAD
|
||||
Running: /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.wdb
|
||||
ISim P.20131013 (signature 0xfbc00daa)
|
||||
WARNING: A WEBPACK license was found.
|
||||
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
|
||||
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
|
||||
This is a Lite version of ISim.
|
||||
=======
|
||||
Running: /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.wdb
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
----------------------------------------------------------------------
|
||||
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
This is a Full version of ISim.
|
||||
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
|
||||
Time resolution is 1 ps
|
||||
# onerror resume
|
||||
# wave add /
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
Finished circuit initialization process.
|
||||
ISim P.20160913 (signature 0xfbc00daa)
|
||||
----------------------------------------------------------------------
|
||||
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
This is a Full version of ISim.
|
||||
# run 1000 ns
|
||||
Simulator is doing circuit initialization process.
|
||||
Finished circuit initialization process.
|
||||
# exit 0
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,28 +0,0 @@
|
||||
Command line:
|
||||
TwoComplementTest_isim_beh.exe
|
||||
-simmode gui
|
||||
-simrunnum 0
|
||||
-socket 59889
|
||||
|
||||
Thu Aug 29 13:06:30 2019
|
||||
|
||||
|
||||
Elaboration Time: 0.13 sec
|
||||
|
||||
Current Memory Usage: 198.607 Meg
|
||||
|
||||
Total Signals : 7
|
||||
Total Nets : 25
|
||||
Total Signal Drivers : 5
|
||||
Total Blocks : 3
|
||||
Total Primitive Blocks : 2
|
||||
Total Processes : 6
|
||||
Total Traceable Variables : 10
|
||||
Total Scalar Nets and Variables : 387
|
||||
|
||||
Total Simulation Time: 0.17 sec
|
||||
|
||||
Current Memory Usage: 276.206 Meg
|
||||
|
||||
Thu Aug 29 13:10:59 2019
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,40 +0,0 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
#include "xsi.h"
|
||||
|
||||
struct XSI_INFO xsi_info;
|
||||
|
||||
char *IEEE_P_2592010699;
|
||||
char *STD_STANDARD;
|
||||
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
xsi_init_design(argc, argv);
|
||||
xsi_register_info(&xsi_info);
|
||||
|
||||
xsi_register_min_prec_unit(-12);
|
||||
ieee_p_2592010699_init();
|
||||
work_a_3935631676_2318913362_init();
|
||||
work_a_2858062612_2372691052_init();
|
||||
|
||||
|
||||
xsi_register_tops("work_a_2858062612_2372691052");
|
||||
|
||||
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
|
||||
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
|
||||
STD_STANDARD = xsi_get_engine_memory("std_standard");
|
||||
|
||||
return xsi_run_simulation(argc, argv);
|
||||
|
||||
}
|
||||
Binary file not shown.
@@ -1,364 +0,0 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0xfbc00daa */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd";
|
||||
|
||||
|
||||
|
||||
static void work_a_2858062612_2372691052_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
char *t4;
|
||||
char *t5;
|
||||
char *t6;
|
||||
int64 t7;
|
||||
int64 t8;
|
||||
|
||||
LAB0: t1 = (t0 + 2624U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(45, ng0);
|
||||
t2 = (t0 + 3504);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)2;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(46, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2432);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(47, ng0);
|
||||
t2 = (t0 + 3504);
|
||||
t3 = (t2 + 56U);
|
||||
t4 = *((char **)t3);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
*((unsigned char *)t6) = (unsigned char)3;
|
||||
xsi_driver_first_trans_fast(t2);
|
||||
xsi_set_current_line(48, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t7 = *((int64 *)t3);
|
||||
t8 = (t7 / 2);
|
||||
t2 = (t0 + 2432);
|
||||
xsi_process_wait(t2, t8);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: goto LAB2;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_2858062612_2372691052_p_1(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
int64 t3;
|
||||
char *t4;
|
||||
int64 t5;
|
||||
|
||||
LAB0: t1 = (t0 + 2872U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(56, ng0);
|
||||
t3 = (100 * 1000LL);
|
||||
t2 = (t0 + 2680);
|
||||
xsi_process_wait(t2, t3);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(58, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t4 = *((char **)t2);
|
||||
t3 = *((int64 *)t4);
|
||||
t5 = (t3 * 10);
|
||||
t2 = (t0 + 2680);
|
||||
xsi_process_wait(t2, t5);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(62, ng0);
|
||||
|
||||
LAB14: *((char **)t1) = &&LAB15;
|
||||
goto LAB1;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
LAB12: goto LAB2;
|
||||
|
||||
LAB13: goto LAB12;
|
||||
|
||||
LAB15: goto LAB13;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_2858062612_2372691052_p_2(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
char *t4;
|
||||
char *t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
char *t8;
|
||||
int64 t9;
|
||||
|
||||
LAB0: t1 = (t0 + 3120U);
|
||||
t2 = *((char **)t1);
|
||||
if (t2 == 0)
|
||||
goto LAB2;
|
||||
|
||||
LAB3: goto *t2;
|
||||
|
||||
LAB2: xsi_set_current_line(67, ng0);
|
||||
t2 = (t0 + 5616);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(68, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB6: *((char **)t1) = &&LAB7;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: xsi_set_current_line(69, ng0);
|
||||
t2 = (t0 + 5624);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(70, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB10: *((char **)t1) = &&LAB11;
|
||||
goto LAB1;
|
||||
|
||||
LAB5: goto LAB4;
|
||||
|
||||
LAB7: goto LAB5;
|
||||
|
||||
LAB8: xsi_set_current_line(71, ng0);
|
||||
t2 = (t0 + 5632);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(72, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB14: *((char **)t1) = &&LAB15;
|
||||
goto LAB1;
|
||||
|
||||
LAB9: goto LAB8;
|
||||
|
||||
LAB11: goto LAB9;
|
||||
|
||||
LAB12: xsi_set_current_line(73, ng0);
|
||||
t2 = (t0 + 5640);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(74, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB18: *((char **)t1) = &&LAB19;
|
||||
goto LAB1;
|
||||
|
||||
LAB13: goto LAB12;
|
||||
|
||||
LAB15: goto LAB13;
|
||||
|
||||
LAB16: xsi_set_current_line(75, ng0);
|
||||
t2 = (t0 + 5648);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(76, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB22: *((char **)t1) = &&LAB23;
|
||||
goto LAB1;
|
||||
|
||||
LAB17: goto LAB16;
|
||||
|
||||
LAB19: goto LAB17;
|
||||
|
||||
LAB20: xsi_set_current_line(77, ng0);
|
||||
t2 = (t0 + 5656);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(78, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB26: *((char **)t1) = &&LAB27;
|
||||
goto LAB1;
|
||||
|
||||
LAB21: goto LAB20;
|
||||
|
||||
LAB23: goto LAB21;
|
||||
|
||||
LAB24: xsi_set_current_line(79, ng0);
|
||||
t2 = (t0 + 5664);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(80, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB30: *((char **)t1) = &&LAB31;
|
||||
goto LAB1;
|
||||
|
||||
LAB25: goto LAB24;
|
||||
|
||||
LAB27: goto LAB25;
|
||||
|
||||
LAB28: xsi_set_current_line(81, ng0);
|
||||
t2 = (t0 + 5672);
|
||||
t4 = (t0 + 3568);
|
||||
t5 = (t4 + 56U);
|
||||
t6 = *((char **)t5);
|
||||
t7 = (t6 + 56U);
|
||||
t8 = *((char **)t7);
|
||||
memcpy(t8, t2, 8U);
|
||||
xsi_driver_first_trans_fast(t4);
|
||||
xsi_set_current_line(82, ng0);
|
||||
t2 = (t0 + 1648U);
|
||||
t3 = *((char **)t2);
|
||||
t9 = *((int64 *)t3);
|
||||
t2 = (t0 + 2928);
|
||||
xsi_process_wait(t2, t9);
|
||||
|
||||
LAB34: *((char **)t1) = &&LAB35;
|
||||
goto LAB1;
|
||||
|
||||
LAB29: goto LAB28;
|
||||
|
||||
LAB31: goto LAB29;
|
||||
|
||||
LAB32: goto LAB2;
|
||||
|
||||
LAB33: goto LAB32;
|
||||
|
||||
LAB35: goto LAB33;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_2858062612_2372691052_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_2858062612_2372691052_p_0,(void *)work_a_2858062612_2372691052_p_1,(void *)work_a_2858062612_2372691052_p_2};
|
||||
xsi_register_didat("work_a_2858062612_2372691052", "isim/TwoComplementTest_isim_beh.exe.sim/work/a_2858062612_2372691052.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,304 +0,0 @@
|
||||
/**********************************************************************/
|
||||
/* ____ ____ */
|
||||
/* / /\/ / */
|
||||
/* /___/ \ / */
|
||||
/* \ \ \/ */
|
||||
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
|
||||
/* / / All Right Reserved. */
|
||||
/* /---/ /\ */
|
||||
/* \ \ / \ */
|
||||
/* \___\/\___\ */
|
||||
/***********************************************************************/
|
||||
|
||||
/* This file is designed for use with ISim build 0xfbc00daa */
|
||||
|
||||
#define XSI_HIDE_SYMBOL_SPEC true
|
||||
#include "xsi.h"
|
||||
#include <memory.h>
|
||||
#ifdef __GNUC__
|
||||
#include <stdlib.h>
|
||||
#else
|
||||
#include <malloc.h>
|
||||
#define alloca _alloca
|
||||
#endif
|
||||
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd";
|
||||
extern char *IEEE_P_2592010699;
|
||||
|
||||
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
|
||||
unsigned char ieee_p_2592010699_sub_3488768497506413324_503743352(char *, unsigned char , unsigned char );
|
||||
|
||||
|
||||
static void work_a_3935631676_2318913362_p_0(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
int t3;
|
||||
int t4;
|
||||
unsigned int t5;
|
||||
unsigned int t6;
|
||||
unsigned int t7;
|
||||
unsigned char t8;
|
||||
char *t9;
|
||||
char *t10;
|
||||
char *t11;
|
||||
char *t12;
|
||||
char *t13;
|
||||
char *t14;
|
||||
|
||||
LAB0: xsi_set_current_line(24, ng0);
|
||||
|
||||
LAB3: t1 = (t0 + 1032U);
|
||||
t2 = *((char **)t1);
|
||||
t3 = (8 - 1);
|
||||
t4 = (t3 - 7);
|
||||
t5 = (t4 * -1);
|
||||
t6 = (1U * t5);
|
||||
t7 = (0 + t6);
|
||||
t1 = (t2 + t7);
|
||||
t8 = *((unsigned char *)t1);
|
||||
t9 = (t0 + 3832);
|
||||
t10 = (t9 + 56U);
|
||||
t11 = *((char **)t10);
|
||||
t12 = (t11 + 56U);
|
||||
t13 = *((char **)t12);
|
||||
*((unsigned char *)t13) = t8;
|
||||
xsi_driver_first_trans_fast(t9);
|
||||
|
||||
LAB2: t14 = (t0 + 3720);
|
||||
*((int *)t14) = 1;
|
||||
|
||||
LAB1: return;
|
||||
LAB4: goto LAB2;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_3935631676_2318913362_p_1(char *t0)
|
||||
{
|
||||
int t1;
|
||||
char *t2;
|
||||
char *t3;
|
||||
int t4;
|
||||
int t5;
|
||||
char *t6;
|
||||
char *t7;
|
||||
unsigned char t8;
|
||||
char *t9;
|
||||
int t10;
|
||||
int t11;
|
||||
unsigned int t12;
|
||||
unsigned int t13;
|
||||
unsigned int t14;
|
||||
char *t15;
|
||||
unsigned char t16;
|
||||
unsigned char t17;
|
||||
char *t18;
|
||||
int t19;
|
||||
int t20;
|
||||
unsigned int t21;
|
||||
unsigned int t22;
|
||||
unsigned int t23;
|
||||
char *t24;
|
||||
char *t25;
|
||||
char *t26;
|
||||
char *t27;
|
||||
char *t28;
|
||||
|
||||
LAB0: xsi_set_current_line(30, ng0);
|
||||
t1 = (8 - 2);
|
||||
t2 = (t0 + 5901);
|
||||
*((int *)t2) = t1;
|
||||
t3 = (t0 + 5905);
|
||||
*((int *)t3) = 0;
|
||||
t4 = t1;
|
||||
t5 = 0;
|
||||
|
||||
LAB2: if (t4 >= t5)
|
||||
goto LAB3;
|
||||
|
||||
LAB5: t2 = (t0 + 3736);
|
||||
*((int *)t2) = 1;
|
||||
|
||||
LAB1: return;
|
||||
LAB3: xsi_set_current_line(31, ng0);
|
||||
t6 = (t0 + 1352U);
|
||||
t7 = *((char **)t6);
|
||||
t8 = *((unsigned char *)t7);
|
||||
t6 = (t0 + 1032U);
|
||||
t9 = *((char **)t6);
|
||||
t6 = (t0 + 5901);
|
||||
t10 = *((int *)t6);
|
||||
t11 = (t10 - 7);
|
||||
t12 = (t11 * -1);
|
||||
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
|
||||
t13 = (1U * t12);
|
||||
t14 = (0 + t13);
|
||||
t15 = (t9 + t14);
|
||||
t16 = *((unsigned char *)t15);
|
||||
t17 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t8, t16);
|
||||
t18 = (t0 + 5901);
|
||||
t19 = *((int *)t18);
|
||||
t20 = (t19 - 6);
|
||||
t21 = (t20 * -1);
|
||||
t22 = (1 * t21);
|
||||
t23 = (0U + t22);
|
||||
t24 = (t0 + 3896);
|
||||
t25 = (t24 + 56U);
|
||||
t26 = *((char **)t25);
|
||||
t27 = (t26 + 56U);
|
||||
t28 = *((char **)t27);
|
||||
*((unsigned char *)t28) = t17;
|
||||
xsi_driver_first_trans_delta(t24, t23, 1, 0LL);
|
||||
|
||||
LAB4: t2 = (t0 + 5901);
|
||||
t4 = *((int *)t2);
|
||||
t3 = (t0 + 5905);
|
||||
t5 = *((int *)t3);
|
||||
if (t4 == t5)
|
||||
goto LAB5;
|
||||
|
||||
LAB6: t1 = (t4 + -1);
|
||||
t4 = t1;
|
||||
t6 = (t0 + 5901);
|
||||
*((int *)t6) = t4;
|
||||
goto LAB2;
|
||||
|
||||
}
|
||||
|
||||
static void work_a_3935631676_2318913362_p_2(char *t0)
|
||||
{
|
||||
char *t1;
|
||||
char *t2;
|
||||
unsigned char t3;
|
||||
char *t4;
|
||||
int t5;
|
||||
int t6;
|
||||
int t7;
|
||||
char *t8;
|
||||
int t9;
|
||||
int t10;
|
||||
unsigned int t11;
|
||||
unsigned int t12;
|
||||
unsigned int t13;
|
||||
char *t14;
|
||||
char *t15;
|
||||
char *t16;
|
||||
unsigned char t17;
|
||||
unsigned char t18;
|
||||
int t19;
|
||||
int t20;
|
||||
unsigned int t21;
|
||||
unsigned int t22;
|
||||
unsigned int t23;
|
||||
char *t24;
|
||||
char *t25;
|
||||
char *t26;
|
||||
char *t27;
|
||||
char *t28;
|
||||
|
||||
LAB0: xsi_set_current_line(42, ng0);
|
||||
t1 = (t0 + 1352U);
|
||||
t2 = *((char **)t1);
|
||||
t3 = *((unsigned char *)t2);
|
||||
t1 = (t0 + 1928U);
|
||||
t4 = *((char **)t1);
|
||||
t1 = (t4 + 0);
|
||||
*((unsigned char *)t1) = t3;
|
||||
xsi_set_current_line(44, ng0);
|
||||
t5 = (8 - 2);
|
||||
t1 = (t0 + 5909);
|
||||
*((int *)t1) = 0;
|
||||
t2 = (t0 + 5913);
|
||||
*((int *)t2) = t5;
|
||||
t6 = 0;
|
||||
t7 = t5;
|
||||
|
||||
LAB2: if (t6 <= t7)
|
||||
goto LAB3;
|
||||
|
||||
LAB5: xsi_set_current_line(49, ng0);
|
||||
t1 = (t0 + 1928U);
|
||||
t2 = *((char **)t1);
|
||||
t3 = *((unsigned char *)t2);
|
||||
t1 = (t0 + 3960);
|
||||
t4 = (t1 + 56U);
|
||||
t8 = *((char **)t4);
|
||||
t14 = (t8 + 56U);
|
||||
t15 = *((char **)t14);
|
||||
*((unsigned char *)t15) = t3;
|
||||
xsi_driver_first_trans_delta(t1, 0U, 1, 0LL);
|
||||
t1 = (t0 + 3752);
|
||||
*((int *)t1) = 1;
|
||||
|
||||
LAB1: return;
|
||||
LAB3: xsi_set_current_line(45, ng0);
|
||||
t4 = (t0 + 1512U);
|
||||
t8 = *((char **)t4);
|
||||
t4 = (t0 + 5909);
|
||||
t9 = *((int *)t4);
|
||||
t10 = (t9 - 6);
|
||||
t11 = (t10 * -1);
|
||||
xsi_vhdl_check_range_of_index(6, 0, -1, *((int *)t4));
|
||||
t12 = (1U * t11);
|
||||
t13 = (0 + t12);
|
||||
t14 = (t8 + t13);
|
||||
t3 = *((unsigned char *)t14);
|
||||
t15 = (t0 + 1928U);
|
||||
t16 = *((char **)t15);
|
||||
t17 = *((unsigned char *)t16);
|
||||
t18 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t3, t17);
|
||||
t15 = (t0 + 5909);
|
||||
t19 = *((int *)t15);
|
||||
t20 = (t19 - 7);
|
||||
t21 = (t20 * -1);
|
||||
t22 = (1 * t21);
|
||||
t23 = (0U + t22);
|
||||
t24 = (t0 + 3960);
|
||||
t25 = (t24 + 56U);
|
||||
t26 = *((char **)t25);
|
||||
t27 = (t26 + 56U);
|
||||
t28 = *((char **)t27);
|
||||
*((unsigned char *)t28) = t18;
|
||||
xsi_driver_first_trans_delta(t24, t23, 1, 0LL);
|
||||
xsi_set_current_line(46, ng0);
|
||||
t1 = (t0 + 1512U);
|
||||
t2 = *((char **)t1);
|
||||
t1 = (t0 + 5909);
|
||||
t5 = *((int *)t1);
|
||||
t9 = (t5 - 6);
|
||||
t11 = (t9 * -1);
|
||||
xsi_vhdl_check_range_of_index(6, 0, -1, *((int *)t1));
|
||||
t12 = (1U * t11);
|
||||
t13 = (0 + t12);
|
||||
t4 = (t2 + t13);
|
||||
t3 = *((unsigned char *)t4);
|
||||
t8 = (t0 + 1928U);
|
||||
t14 = *((char **)t8);
|
||||
t17 = *((unsigned char *)t14);
|
||||
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t17);
|
||||
t8 = (t0 + 1928U);
|
||||
t15 = *((char **)t8);
|
||||
t8 = (t15 + 0);
|
||||
*((unsigned char *)t8) = t18;
|
||||
|
||||
LAB4: t1 = (t0 + 5909);
|
||||
t6 = *((int *)t1);
|
||||
t2 = (t0 + 5913);
|
||||
t7 = *((int *)t2);
|
||||
if (t6 == t7)
|
||||
goto LAB5;
|
||||
|
||||
LAB6: t5 = (t6 + 1);
|
||||
t6 = t5;
|
||||
t4 = (t0 + 5909);
|
||||
*((int *)t4) = t6;
|
||||
goto LAB2;
|
||||
|
||||
}
|
||||
|
||||
|
||||
extern void work_a_3935631676_2318913362_init()
|
||||
{
|
||||
static char *pe[] = {(void *)work_a_3935631676_2318913362_p_0,(void *)work_a_3935631676_2318913362_p_1,(void *)work_a_3935631676_2318913362_p_2};
|
||||
xsi_register_didat("work_a_3935631676_2318913362", "isim/TwoComplementTest_isim_beh.exe.sim/work/a_3935631676_2318913362.didat");
|
||||
xsi_register_executes(pe);
|
||||
}
|
||||
Binary file not shown.
Binary file not shown.
@@ -1,16 +0,0 @@
|
||||
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
|
||||
<xtag-section name="ISimStatistics">
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>2400 ms, 103960 KB</xtag-isim-property-value></TD></TR>
|
||||
|
||||
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>25</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.17 sec, 275152 KB</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
|
||||
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
|
||||
</xtag-section>
|
||||
</TABLE>
|
||||
@@ -1 +0,0 @@
|
||||
14.7
|
||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
15
pa.fromNcd.tcl
Normal file
15
pa.fromNcd.tcl
Normal file
@@ -0,0 +1,15 @@
|
||||
|
||||
# PlanAhead Launch Script for Post PAR Floorplanning, created by Project Navigator
|
||||
|
||||
create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
|
||||
set srcset [get_property srcset [current_run -impl]]
|
||||
set_property design_mode GateLvl $srcset
|
||||
set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
|
||||
add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
|
||||
set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
|
||||
add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
|
||||
link_design
|
||||
read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
|
||||
if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
|
||||
puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
|
||||
}
|
||||
12
planAhead.ngc2edif.log
Normal file
12
planAhead.ngc2edif.log
Normal file
@@ -0,0 +1,12 @@
|
||||
Release 14.7 - ngc2edif P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
Reading design SpecialCasesCheck.ngc ...
|
||||
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
|
||||
ignored.
|
||||
Processing design ...
|
||||
Preping design's networks ...
|
||||
Preping design's macros ...
|
||||
finished :Prep
|
||||
Writing EDIF netlist file SpecialCasesCheck.edif ...
|
||||
ngc2edif: Total memory usage is 103004 kilobytes
|
||||
|
||||
92
planAhead_pid7025.debug
Normal file
92
planAhead_pid7025.debug
Normal file
@@ -0,0 +1,92 @@
|
||||
#-------------------------------------------------------------------------------
|
||||
# PlanAhead v14.7 (64-bit)
|
||||
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
|
||||
# Current time: 8/24/19 2:52:26 PM
|
||||
# Process ID: 7025
|
||||
# Platform: Unix
|
||||
#
|
||||
# This file is an indication that an internal application error occurred.
|
||||
# This information is useful for debugging. Please open a case with Xilinx
|
||||
# Technical Support with this file and a testcase attached.
|
||||
#-------------------------------------------------------------------------------
|
||||
8/24/19 2:52:26 PM
|
||||
ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
|
||||
HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
|
||||
HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
|
||||
HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
|
||||
HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
|
||||
|
||||
at ui.h.e.CF(SourceFile:217)
|
||||
at ui.h.I.CF(SourceFile:702)
|
||||
at ui.frmwork.HTclEventBroker.a(SourceFile:368)
|
||||
at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
|
||||
at ui.project.a.een(SourceFile:759)
|
||||
at ui.project.a.cleanup(SourceFile:608)
|
||||
at ui.project.r.cleanup(SourceFile:631)
|
||||
at ui.PlanAhead.aJj(SourceFile:335)
|
||||
at ui.PlanAhead.a(SourceFile:1192)
|
||||
at ui.frmwork.a.i.c(SourceFile:35)
|
||||
at ui.frmwork.HTclEventBroker.a(SourceFile:233)
|
||||
at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
|
||||
at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
|
||||
at ui.e.gY(SourceFile:195)
|
||||
at ui.bl.run(SourceFile:882)
|
||||
at ui.cd.run(SourceFile:1821)
|
||||
at ui.views.F.aw.a(SourceFile:341)
|
||||
at ui.cd.b(SourceFile:1809)
|
||||
at ui.cd.a(SourceFile:1784)
|
||||
at ui.PlanAhead.a(SourceFile:778)
|
||||
at ui.aL.c(SourceFile:885)
|
||||
at ui.aL.aHs(SourceFile:824)
|
||||
at ui.bk.windowClosing(SourceFile:503)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
|
||||
at java.awt.Window.processWindowEvent(Window.java:2051)
|
||||
at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
|
||||
at java.awt.Window.processEvent(Window.java:2009)
|
||||
at ui.aL.processEvent(SourceFile:1214)
|
||||
at java.awt.Component.dispatchEventImpl(Component.java:4861)
|
||||
at java.awt.Container.dispatchEventImpl(Container.java:2287)
|
||||
at java.awt.Window.dispatchEventImpl(Window.java:2719)
|
||||
at java.awt.Component.dispatchEvent(Component.java:4687)
|
||||
at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
|
||||
at java.awt.EventQueue.access$200(EventQueue.java:103)
|
||||
at java.awt.EventQueue$3.run(EventQueue.java:688)
|
||||
at java.awt.EventQueue$3.run(EventQueue.java:686)
|
||||
at java.security.AccessController.doPrivileged(Native Method)
|
||||
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
|
||||
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
|
||||
at java.awt.EventQueue$4.run(EventQueue.java:702)
|
||||
at java.awt.EventQueue$4.run(EventQueue.java:700)
|
||||
at java.security.AccessController.doPrivileged(Native Method)
|
||||
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
|
||||
at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
|
||||
at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
|
||||
at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
|
||||
at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
|
||||
at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
|
||||
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
|
||||
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
|
||||
at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)
|
||||
|
||||
1762
planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif
vendored
Normal file
1762
planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif
vendored
Normal file
File diff suppressed because it is too large
Load Diff
16
planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml
Normal file
16
planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml
Normal file
@@ -0,0 +1,16 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../SpecialCasesCheck.ucf">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PPRDIR/../SpecialCasesCheck.ucf"/>
|
||||
<Option Name="ConstrsType" Val="UCF"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</DARoots>
|
||||
20
planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg
Normal file
20
planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg
Normal file
@@ -0,0 +1,20 @@
|
||||
<?xml version="1.0"?>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="ISE Defaults" Flow="ISE14">
|
||||
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="ngdbuild">
|
||||
</Step>
|
||||
<Step Id="map">
|
||||
<Option Id="FFPackEnum">3</Option>
|
||||
</Step>
|
||||
<Step Id="par">
|
||||
</Step>
|
||||
<Step Id="trce">
|
||||
</Step>
|
||||
<Step Id="xdl">
|
||||
</Step>
|
||||
<Step Id="bitgen">
|
||||
</Step>
|
||||
</Strategy>
|
||||
|
||||
5
planAhead_run_1/IEEE754Adder.data/runs/runs.xml
Normal file
5
planAhead_run_1/IEEE754Adder.data/runs/runs.xml
Normal file
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="8">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xa6slx4csg225-3" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
|
||||
</Runs>
|
||||
|
||||
10
planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml
Normal file
10
planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</DARoots>
|
||||
30
planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml
Normal file
30
planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml
Normal file
@@ -0,0 +1,30 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="EDIFSrcs"/>
|
||||
<File Path="$PPRDIR/../SpecialCasesCheck.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../equalCheck.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../TypeCheck.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="GateLvl"/>
|
||||
<Option Name="GateLvlMode" Val="EDIF"/>
|
||||
<Option Name="TopFile" Val="$PPRDIR/../SpecialCasesCheck.ngc"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</DARoots>
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:35:00:00
|
||||
eof:3762079013
|
||||
4
planAhead_run_1/IEEE754Adder.data/wt/project.wpc
Normal file
4
planAhead_run_1/IEEE754Adder.data/wt/project.wpc
Normal file
@@ -0,0 +1,4 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
6d6f64655f636f756e7465727c4953454d6f6465:1
|
||||
eof:
|
||||
29
planAhead_run_1/IEEE754Adder.data/wt/webtalk_pa.xml
Normal file
29
planAhead_run_1/IEEE754Adder.data/wt/webtalk_pa.xml
Normal file
@@ -0,0 +1,29 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sat Aug 24 14:52:23 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="e7a017e01966464abdfa199c35ad33a2" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="GateLvl" type="DesignMode"/>
|
||||
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="ZoomIn" value="5" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="0" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="0" type="TclMode"/>
|
||||
<property name="ISEMode" value="1" type="ISEMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
28
planAhead_run_1/IEEE754Adder.ppr
Normal file
28
planAhead_run_1/IEEE754Adder.ppr
Normal file
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0"?>
|
||||
<!--Product Version: PlanAhead v14.7 (64-bit)-->
|
||||
<Project Version="4" Minor="36">
|
||||
<FileSet Dir="sources_1" File="fileset.xml"/>
|
||||
<FileSet Dir="constrs_1" File="fileset.xml"/>
|
||||
<FileSet Dir="sim_1" File="fileset.xml"/>
|
||||
<RunSet Dir="runs" File="runs.xml"/>
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<DefaultPromote Dir="$PROMOTEDIR"/>
|
||||
<Config>
|
||||
<Option Name="Id" Val="45689c7b25ae425b84c8ab3f166c9430"/>
|
||||
<Option Name="Part" Val="xa6slx4csg225-3"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="TargetLanguage" Val="Verilog"/>
|
||||
<Option Name="TargetSimulator" Val="ISim"/>
|
||||
<Option Name="Board" Val=""/>
|
||||
<Option Name="SourceMgmtMode" Val="All"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="CxlOverwriteLibs" Val="1"/>
|
||||
<Option Name="CxlFuncsim" Val="1"/>
|
||||
<Option Name="CxlTimesim" Val="1"/>
|
||||
<Option Name="CxlCore" Val="1"/>
|
||||
<Option Name="CxlEdk" Val="0"/>
|
||||
<Option Name="CxlExcludeCores" Val="1"/>
|
||||
<Option Name="CxlExcludeSubLibs" Val="0"/>
|
||||
</Config>
|
||||
</Project>
|
||||
|
||||
10
planAhead_run_1/planAhead.jou
Normal file
10
planAhead_run_1/planAhead.jou
Normal file
@@ -0,0 +1,10 @@
|
||||
#-----------------------------------------------------------
|
||||
# PlanAhead v14.7 (64-bit)
|
||||
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
|
||||
# Start of session at: Sat Aug 24 14:51:32 2019
|
||||
# Process ID: 7025
|
||||
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
|
||||
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
|
||||
#-----------------------------------------------------------
|
||||
start_gui
|
||||
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
|
||||
83
planAhead_run_1/planAhead.log
Normal file
83
planAhead_run_1/planAhead.log
Normal file
@@ -0,0 +1,83 @@
|
||||
#-----------------------------------------------------------
|
||||
# PlanAhead v14.7 (64-bit)
|
||||
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
|
||||
# Start of session at: Sat Aug 24 14:51:32 2019
|
||||
# Process ID: 7025
|
||||
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
|
||||
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
|
||||
#-----------------------------------------------------------
|
||||
INFO: [Common 17-78] Attempting to get a license: PlanAhead
|
||||
INFO: [Common 17-290] Got license for PlanAhead
|
||||
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
|
||||
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
||||
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
||||
start_gui
|
||||
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
|
||||
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
|
||||
# set srcset [get_property srcset [current_run -impl]]
|
||||
# set_property design_mode GateLvl $srcset
|
||||
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
|
||||
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
|
||||
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
|
||||
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
|
||||
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
|
||||
# link_design
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
Design is defaulting to project part: xa6slx4csg225-3
|
||||
Release 14.7 - ngc2edif P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Release 14.7 - ngc2edif P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
Reading design SpecialCasesCheck.ngc ...
|
||||
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
|
||||
ignored.
|
||||
Processing design ...
|
||||
Preping design's networks ...
|
||||
Preping design's macros ...
|
||||
finished :Prep
|
||||
Writing EDIF netlist file SpecialCasesCheck.edif ...
|
||||
ngc2edif: Total memory usage is 103004 kilobytes
|
||||
|
||||
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
|
||||
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
|
||||
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
|
||||
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
|
||||
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
|
||||
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
|
||||
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
|
||||
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
|
||||
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
|
||||
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
|
||||
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Phase 0 | Netlist Checksum: 684e9dfa
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
|
||||
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
|
||||
Release 14.7 - xdl P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
|
||||
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
|
||||
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
|
||||
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
|
||||
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
|
||||
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
|
||||
INFO: [Designutils 20-671] Placed 103 instances
|
||||
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
|
||||
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
|
||||
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
|
||||
# }
|
||||
exit
|
||||
ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
|
||||
HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
|
||||
HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
|
||||
HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
|
||||
HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
|
||||
(See /home/Luca/ISE/IEEE754Adder/planAhead_pid7025.debug)
|
||||
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
|
||||
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
|
||||
INFO: [Common 17-83] Releasing license: PlanAhead
|
||||
74
planAhead_run_1/planAhead_run.log
Normal file
74
planAhead_run_1/planAhead_run.log
Normal file
@@ -0,0 +1,74 @@
|
||||
|
||||
****** PlanAhead v14.7 (64-bit)
|
||||
**** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
|
||||
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
INFO: [Common 17-78] Attempting to get a license: PlanAhead
|
||||
INFO: [Common 17-290] Got license for PlanAhead
|
||||
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
|
||||
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
||||
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
|
||||
start_gui
|
||||
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
|
||||
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
|
||||
# set srcset [get_property srcset [current_run -impl]]
|
||||
# set_property design_mode GateLvl $srcset
|
||||
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
|
||||
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
|
||||
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
|
||||
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
|
||||
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
|
||||
# link_design
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
Design is defaulting to project part: xa6slx4csg225-3
|
||||
Release 14.7 - ngc2edif P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Release 14.7 - ngc2edif P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
Reading design SpecialCasesCheck.ngc ...
|
||||
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
|
||||
ignored.
|
||||
Processing design ...
|
||||
Preping design's networks ...
|
||||
Preping design's macros ...
|
||||
finished :Prep
|
||||
Writing EDIF netlist file SpecialCasesCheck.edif ...
|
||||
ngc2edif: Total memory usage is 103004 kilobytes
|
||||
|
||||
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
|
||||
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
|
||||
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
|
||||
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
|
||||
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
|
||||
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
|
||||
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
|
||||
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
|
||||
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
|
||||
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
|
||||
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Phase 0 | Netlist Checksum: 684e9dfa
|
||||
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
|
||||
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
|
||||
Release 14.7 - xdl P.20131013 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
|
||||
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
|
||||
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
|
||||
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
|
||||
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
|
||||
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
|
||||
INFO: [Designutils 20-671] Placed 103 instances
|
||||
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
|
||||
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
|
||||
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
|
||||
# }
|
||||
exit
|
||||
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
|
||||
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
|
||||
INFO: [Common 17-83] Releasing license: PlanAhead
|
||||
Reference in New Issue
Block a user