diff --git a/Comparator.vhd b/Comparator.vhd
index 37e3688..338fab0 100644
--- a/Comparator.vhd
+++ b/Comparator.vhd
@@ -3,31 +3,43 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is
- generic( BITCOUNT: integer := 8 );
+
+ generic( BITCOUNT : integer := 8 );
+
port(
- xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
- needSwap: out std_logic
+ X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
+ NEED_SWAP : out std_logic
);
+
end Comparator;
architecture ComparatorArch of Comparator is
- signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
- signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
-begin
- xGTy <= xT and (not yT);
- yGTx <= (not xT) and yT;
+
+ signal X_GT_Y : std_logic_vector((BITCOUNT-1) downto 0);
+ signal Y_GT_X : std_logic_vector((BITCOUNT-1) downto 0);
+
+begin
+
+ X_GT_Y <= X_MANT and (not Y_MANT);
+ Y_GT_X <= (not X_MANT) and Y_MANT;
+
+ NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
+
+ variable SWAP : std_logic;
+ variable SWAP_CARRY : std_logic;
- needSwap_compute: process (xGTy, yGTx)
- variable SW: std_logic;
- variable K: std_logic;
begin
- SW := '0';
- K := '1';
+
+ SWAP := '0';
+ SWAP_CARRY := '1';
+
for i in (BITCOUNT-1) downto 0 loop
- SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
- K := K and (not(xGTy(i) and not(yGTx(i))));
+ SWAP := SWAP or ((not(X_GT_Y(i)) and Y_GT_X(i)) and SWAP_CARRY);
+ SWAP_CARRY := SWAP_CARRY and (not(X_GT_Y(i) and not(Y_GT_X(i))));
end loop;
- needSwap <= SW;
+
+ NEED_SWAP <= SWAP;
+
end process;
end ComparatorArch;
diff --git a/EqualCheck.vhd b/EqualCheck.vhd
index 15cd1ba..7e50fc8 100644
--- a/EqualCheck.vhd
+++ b/EqualCheck.vhd
@@ -1,28 +1,42 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
- isEqual: out std_logic
- );
-end EqualCheck;
-
-architecture EqualCheckArch of EqualCheck is
- signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
-begin
- compVec <= X xor Y;
-
- res_compute: process (compVec)
- variable res_tmp: std_logic;
- begin
- res_tmp := '0';
- for i in compVec'range loop
- res_tmp := res_tmp or compVec(i);
- end loop;
- isEqual <= not res_tmp;
- end process;
-
-end EqualCheckArch;
-
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity EqualCheck is
+
+ generic(
+ BITCOUNT: integer := 8
+ );
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_EQUAL : out std_logic
+ );
+
+end EqualCheck;
+
+architecture EqualCheckArch of EqualCheck is
+
+ signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
+
+begin
+
+ COMP_VEC <= X xor Y;
+
+ RES_COMPUTE: process (COMP_VEC)
+
+ variable RES_TMP : std_logic;
+
+ begin
+
+ RES_TMP := '0';
+
+ for i in COMP_VEC'range loop
+ RES_TMP := RES_TMP or COMP_VEC(i);
+ end loop;
+
+ IS_EQUAL <= not RES_TMP;
+
+ end process;
+
+end EqualCheckArch;
+
diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index 05c84e2..84a5638 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -66,22 +66,18 @@
-
+
-
-
-
-
-
-
-
-
-
+
+
+
+
+
@@ -153,7 +149,7 @@
-
+
@@ -315,6 +311,7 @@
+
@@ -356,6 +353,8 @@
+
+
@@ -375,6 +374,7 @@
+
@@ -431,6 +431,7 @@
+
diff --git a/NaNCheck.vhd b/NaNCheck.vhd
index 1ba7ed4..2f7bd3d 100644
--- a/NaNCheck.vhd
+++ b/NaNCheck.vhd
@@ -2,37 +2,44 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NaNCheck is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- isNan: out std_logic
+ X, Y : in std_logic_vector(31 downto 0);
+ IS_NAN : out std_logic
);
+
end NaNCheck;
architecture NaNCheckArch of NaNCheck is
+
component TypeCheck is
+
port(
- N: in std_logic_vector(31 downto 0);
- NaN, INF: out std_logic
+ N : in std_logic_vector(30 downto 0);
+ NAN, INF : out std_logic
);
+
end component;
- signal xNan: std_logic;
- signal xInf: std_logic;
- signal xSign: std_logic;
- signal yNan: std_logic;
- signal yInf: std_logic;
- signal ySign: std_logic;
+ signal X_NAN : std_logic;
+ signal X_INF : std_logic;
+ signal X_SIGN : std_logic;
+ signal Y_NAN : std_logic;
+ signal Y_INF : std_logic;
+ signal Y_SIGN : std_logic;
begin
- xCheck: TypeCheck
- port map (N => X, NaN => xNan, INF => xInf);
- yCheck: TypeCheck
- port map (N => Y, NaN => yNan, INF => yInf);
- xSign <= X(31);
- ySign <= Y(31);
+ xCheck: TypeCheck
+ port map (N => X(30 downto 0), NAN => X_NAN, INF => X_INF);
+
+ yCheck: TypeCheck
+ port map (N => Y(30 downto 0), NAN => Y_NAN, INF => Y_INF);
+
+ X_SIGN <= X(31);
+ Y_SIGN <= Y(31);
- isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
+ IS_NAN <= X_NAN or Y_NAN or (X_INF and X_SIGN and Y_INF and (not Y_SIGN)) or (X_INF and (not X_SIGN) and Y_INF and Y_SIGN);
end NaNCheckArch;
diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd
index 4c056fd..231ef01 100644
--- a/SpecialCasesCheck.vhd
+++ b/SpecialCasesCheck.vhd
@@ -2,32 +2,43 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SpecialCasesCheck is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- isNaN, isZero: out std_logic
+ X, Y : in std_logic_vector(31 downto 0);
+ IS_NAN, IS_ZERO : out std_logic
);
+
end SpecialCasesCheck;
architecture SpecialCasesCheckArch of SpecialCasesCheck is
+
component NaNCheck is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- isNaN: out std_logic
+ X, Y : in std_logic_vector(31 downto 0);
+ IS_NAN : out std_logic
);
+
end component;
component ZeroCheck is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- isZero: out std_logic
+ X, Y : in std_logic_vector(31 downto 0);
+ IS_ZERO : out std_logic
);
+
end component;
+
begin
+
NC: NaNCheck
- port map (X => X, Y => Y, isNaN => isNaN);
+ port map (X => X, Y => Y, IS_NAN => IS_NAN);
+
ZC: ZeroCheck
- port map (X => X, Y => Y, isZero => isZero);
+ port map (X => X, Y => Y, IS_ZERO => IS_ZERO);
+
end SpecialCasesCheckArch;
diff --git a/Swap.vhd b/Swap.vhd
index 2320648..35bc370 100644
--- a/Swap.vhd
+++ b/Swap.vhd
@@ -2,25 +2,32 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Swap is
- generic(BITCOUNT : integer := 8);
+
+ generic(
+ BITCOUNT : integer := 8
+ );
+
port(
X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
SW : in std_logic;
X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
);
+
end Swap;
architecture SwapArch of Swap is
begin
- SWAP_PRO: process(X_IN, Y_IN, SW)
+
+ SWAP_PROCESS: process(X_IN, Y_IN, SW)
+
begin
+
for i in (BITCOUNT-1) downto 0 loop
-
X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i));
Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i));
-
end loop;
+
end process;
end SwapArch;
diff --git a/TwoComplement.vhd b/TwoComplement.vhd
index 686dff6..4877bd8 100644
--- a/TwoComplement.vhd
+++ b/TwoComplement.vhd
@@ -2,30 +2,53 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TwoComplement is
- generic(BITCOUNT : integer := 8);
+
+ generic(
+ BITCOUNT : integer := 8
+ );
+
port(
DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
- DIFF_EXP_ABS : out std_logic_vector((BITCOUNT-2) downto 0)
+ DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
);
+
end TwoComplement;
architecture TwoComplementArch of TwoComplement is
- signal S : std_logic;
- signal M : std_logic_vector((BITCOUNT-2) downto 0);
-begin
- S <= DIFF_EXP_C2(BITCOUNT-1);
- M <= DIFF_EXP_C2((BITCOUNT-2) downto 0);
+
+ signal SIGN : std_logic;
+ signal DIFF_EXP_ABS : std_logic_vector((BITCOUNT-2) downto 0);
+
+begin
+
+ SIGN <= DIFF_EXP_C2(BITCOUNT-1);
+
+ C2_PROCESS : process(DIFF_EXP_C2, SIGN)
- C2 : process(DIFF_EXP_C2)
begin
+
for i in (BITCOUNT-2) downto 0 loop
- M(i) <= S xor M(i);
+ DIFF_EXP_ABS(i) <= SIGN xor DIFF_EXP_C2(i);
end loop;
+
end process;
- --sommare 1 a M se S = '1'
+ SUM : process(DIFF_EXP_ABS, SIGN)
- DIFF_EXP_ABS <= M;
+ variable CARRY : std_logic;
+
+ begin
+
+ CARRY := SIGN;
+
+ for i in 0 to (BITCOUNT-2) loop
+ DIFF_EXP(i) <= DIFF_EXP_ABS(i) xor CARRY;
+ CARRY := DIFF_EXP_ABS(i) and CARRY;
+ end loop;
+
+ DIFF_EXP(BITCOUNT-1) <= CARRY;
+
+ end process;
end TwoComplementArch;
diff --git a/TwoComplementTest.vhd b/TwoComplementTest.vhd
new file mode 100644
index 0000000..5192b81
--- /dev/null
+++ b/TwoComplementTest.vhd
@@ -0,0 +1,85 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY TwoComplementTest IS
+END TwoComplementTest;
+
+ARCHITECTURE behavior OF TwoComplementTest IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT TwoComplement
+ PORT(
+ DIFF_EXP_C2 : IN std_logic_vector(7 downto 0);
+ DIFF_EXP : OUT std_logic_vector(7 downto 0)
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000";
+
+ --Outputs
+ signal DIFF_EXP : std_logic_vector(7 downto 0);
+ signal clock : std_logic;
+ -- No clocks detected in port list. Replace clock below with
+ -- appropriate port name
+
+ constant clock_period : time := 10 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: TwoComplement PORT MAP (
+ DIFF_EXP_C2 => DIFF_EXP_C2,
+ DIFF_EXP => DIFF_EXP
+ );
+
+ -- Clock process definitions
+ clock_process :process
+ begin
+ clock <= '0';
+ wait for clock_period/2;
+ clock <= '1';
+ wait for clock_period/2;
+ end process;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for clock_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+ test_process :process
+ begin
+ DIFF_EXP_C2 <= "01001110";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "11111111";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "10000000";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "01111111";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "01100101";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "10011101";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "11100010";
+ wait for clock_period;
+ DIFF_EXP_C2 <= "10010011";
+ wait for clock_period;
+ end process;
+
+END;
diff --git a/TwoComplementTest_isim_beh.exe b/TwoComplementTest_isim_beh.exe
new file mode 100644
index 0000000..11ae4f7
Binary files /dev/null and b/TwoComplementTest_isim_beh.exe differ
diff --git a/TwoComplementTest_isim_beh.wdb b/TwoComplementTest_isim_beh.wdb
new file mode 100644
index 0000000..23dc2a8
Binary files /dev/null and b/TwoComplementTest_isim_beh.wdb differ
diff --git a/TypeCheck.vhd b/TypeCheck.vhd
index 8d95d1e..77b4d20 100644
--- a/TypeCheck.vhd
+++ b/TypeCheck.vhd
@@ -2,42 +2,60 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TypeCheck is
+
port(
- N: in std_logic_vector(31 downto 0);
- NaN, INF: out std_logic
+ N : in std_logic_vector(30 downto 0);
+ NAN, INF : out std_logic
);
+
end TypeCheck;
architecture TypeCheckArch of TypeCheck is
- signal G_Bus: std_logic_vector(7 downto 0);
- signal T_Bus: std_logic_vector(22 downto 0);
- signal G: std_logic := '1';
- signal T: std_logic := '0';
+
+ signal G_BUS : std_logic_vector(7 downto 0);
+ signal T_BUS : std_logic_vector(22 downto 0);
+ signal G : std_logic := '1';
+ signal T : std_logic := '0';
+
begin
- G_Bus <= N(30 downto 23);
- T_Bus <= N(22 downto 0);
+
+ G_BUS <= N(30 downto 23);
+ T_BUS <= N(22 downto 0);
- G_compute: process (G_Bus)
- variable G_tmp: std_logic;
+ G_compute: process (G_BUS)
+
+ variable G_TMP : std_logic;
+
begin
- G_tmp := '1';
- for i in G_Bus'range loop
- G_tmp := G_tmp and G_Bus(i);
+
+ G_TMP := '1';
+
+ for i in G_BUS'range loop
+ G_TMP := G_TMP and G_BUS(i);
end loop;
- G <= G_tmp;
+
+ G <= G_TMP;
+
end process;
- T_compute: process (T_Bus)
- variable T_tmp: std_logic;
+ T_compute: process (T_BUS)
+
+ variable T_TMP : std_logic;
+
begin
- T_tmp := '0';
- for i in T_Bus'range loop
- T_tmp := T_tmp or T_Bus(i);
+
+ T_TMP := '0';
+
+ for i in T_BUS'range loop
+ T_TMP := T_TMP or T_BUS(i);
end loop;
- T <= T_tmp;
+
+ T <= T_TMP;
+
end process;
- NaN <= G and T;
+ NAN <= G and T;
INF <= G and (not T);
+
end TypeCheckArch;
diff --git a/ZeroCheck.vhd b/ZeroCheck.vhd
index e13ff55..78b151c 100644
--- a/ZeroCheck.vhd
+++ b/ZeroCheck.vhd
@@ -3,38 +3,50 @@ use IEEE.STD_LOGIC_1164.ALL;
entity ZeroCheck is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- isZero: out std_logic
+ X, Y : in std_logic_vector(31 downto 0);
+ IS_ZERO : out std_logic
);
+
end ZeroCheck;
architecture ZeroCheckArch of ZeroCheck is
+
component EqualCheck is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
- isEqual: out std_logic
+
+ generic(
+ BITCOUNT : integer := 8
);
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_EQUAL : out std_logic
+ );
+
end component;
- signal xSign: std_logic;
- signal ySign: std_logic;
- signal xAbs: std_logic_vector(30 downto 0);
- signal yAbs: std_logic_vector(30 downto 0);
- signal isSameAbsValue: std_logic;
- signal isSameSign: std_logic;
+ signal S_SIGN : std_logic;
+ signal Y_SIGN : std_logic;
+ signal X_ABS : std_logic_vector(30 downto 0);
+ signal Y_ABS : std_logic_vector(30 downto 0);
+ signal IS_SAME_ABS_VALUE : std_logic;
+ signal IS_SAME_SIGN : std_logic;
+
begin
- xSign <= X(31);
- ySign <= Y(31);
- xAbs <= X(30 downto 0);
- yAbs <= Y(30 downto 0);
- isSameSign <= xSign xnor ySign;
+ S_SIGN <= X(31);
+ Y_SIGN <= Y(31);
+ X_ABS <= X(30 downto 0);
+ Y_ABS <= Y(30 downto 0);
+
+ IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
+
AbsCheck: EqualCheck
generic map ( BITCOUNT => 31 )
- port map (X => xAbs, Y => yAbs, isEqual => isSameAbsValue);
+ port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);
+
+ IS_ZERO <= (not IS_SAME_SIGN) and IS_SAME_ABS_VALUE;
- isZero <= (not isSameSign) and isSameAbsValue;
end ZeroCheckArch;
diff --git a/equalCheck.vhd b/equalCheck.vhd
deleted file mode 100644
index 15cd1ba..0000000
--- a/equalCheck.vhd
+++ /dev/null
@@ -1,28 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
- isEqual: out std_logic
- );
-end EqualCheck;
-
-architecture EqualCheckArch of EqualCheck is
- signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
-begin
- compVec <= X xor Y;
-
- res_compute: process (compVec)
- variable res_tmp: std_logic;
- begin
- res_tmp := '0';
- for i in compVec'range loop
- res_tmp := res_tmp or compVec(i);
- end loop;
- isEqual <= not res_tmp;
- end process;
-
-end EqualCheckArch;
-
diff --git a/fuse.log b/fuse.log
index a4151c7..b6e5b65 100644
--- a/fuse.log
+++ b/fuse.log
@@ -1,24 +1,21 @@
-Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj work.AddSubTest
-ISim P.20131013 (signature 0xfbc00daa)
-Number of CPUs detected in this system: 4
-Turning on mult-threading, number of parallel sub-compilation jobs: 8
+Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest
+ISim P.20160913 (signature 0xfbc00daa)
+Number of CPUs detected in this system: 1
+Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSubTest.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work
Starting static elaboration
Completed static elaboration
-Fuse Memory Usage: 94376 KB
-Fuse CPU Usage: 1040 ms
+Fuse Memory Usage: 95308 KB
+Fuse CPU Usage: 2300 ms
Compiling package standard
Compiling package std_logic_1164
-Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
-Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
-Compiling architecture behavior of entity addsubtest
+Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
+Compiling architecture behavior of entity twocomplementtest
Time Resolution for simulation is 1ps.
-Waiting for 1 sub-compilation(s) to finish...
-Compiled 7 VHDL Units
-Built simulation executable /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe
-Fuse Memory Usage: 658004 KB
-Fuse CPU Usage: 1060 ms
-GCC CPU Usage: 210 ms
+Compiled 5 VHDL Units
+Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
+Fuse Memory Usage: 103960 KB
+Fuse CPU Usage: 2400 ms
+GCC CPU Usage: 1480 ms
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
index 1e914c4..07c2c4c 100644
--- a/fuseRelaunch.cmd
+++ b/fuseRelaunch.cmd
@@ -1 +1 @@
--intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj" "work.AddSubTest"
+-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest"
diff --git a/isim.log b/isim.log
index 28eb907..e1e823f 100644
--- a/isim.log
+++ b/isim.log
@@ -1,10 +1,12 @@
ISim log file
-Running: /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.wdb
-ISim P.20131013 (signature 0xfbc00daa)
-WARNING: A WEBPACK license was found.
-WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
-WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
-This is a Lite version of ISim.
+Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb
+ISim P.20160913 (signature 0xfbc00daa)
+----------------------------------------------------------------------
+WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
+
+
+----------------------------------------------------------------------
+This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /