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Completato check casi speciali + test

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This commit is contained in:
Luca Cuzzocrea
2019-08-24 14:39:01 +02:00
parent cd358fae35
commit c6ef95462a
143 changed files with 21122 additions and 224 deletions
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28
EqualCheck.vhd Normal file
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@@ -0,0 +1,28 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EqualCheck is
generic( BITCOUNT: integer := 8 );
port(
X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
isEqual: out std_logic
);
end EqualCheck;
architecture EqualCheckArch of EqualCheck is
signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
begin
compVec <= X xor Y;
res_compute: process (compVec)
variable res_tmp: std_logic;
begin
res_tmp := '0';
for i in compVec'range loop
res_tmp := res_tmp or compVec(i);
end loop;
isEqual <= not res_tmp;
end process;
end EqualCheckArch;

182
IEEE754Adder.gise
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@@ -22,18 +22,52 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="IEEE754Adder.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="NaNCheck_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="NaNCheck_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="SpecialCasesCheck.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="SpecialCasesCheck.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="SpecialCasesCheck.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SpecialCasesCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="SpecialCasesCheck.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SpecialCasesCheck.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SpecialCasesCheck.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="SpecialCasesCheck.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SpecialCasesCheck.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="SpecialCasesCheck.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="SpecialCasesCheck.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="SpecialCasesCheck.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="SpecialCasesCheck.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SpecialCasesCheck.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SpecialCasesCheck.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="SpecialCasesCheck.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="SpecialCasesCheck.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="SpecialCasesCheck.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="SpecialCasesCheck.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="SpecialCasesCheck.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SpecialCasesCheck.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_envsettings.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="SpecialCasesCheck_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SpecialCasesCheck_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SpecialCasesCheck_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SpecialCasesCheck_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SpecialCasesCheck_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SpecialCasesCheck_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="SpecialCasesCheck_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="SpecialCasesCheck_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesTest_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SpecialCasesTest_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="SpecialCasesTest_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesTest_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="TypeCheck.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="TypeCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="TypeCheck.lso"/>
@@ -59,7 +93,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="TypeCheck_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="TypeCheck_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="TypeCheck_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="TypeCheck_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_par.xrpt"/>
@@ -68,12 +101,34 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TypeCheck_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="equalCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="equalCheck.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="equalCheck.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="equalCheck.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="equalCheck.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="equalCheck.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="equalCheck.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="equalCheck.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="equalCheck_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="equalCheck_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="equalCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="netgen"/>
<file xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/synthesis/SpecialCasesCheck_synthesis.nlf"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/synthesis/SpecialCasesCheck_synthesis.vhd"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
@@ -83,38 +138,97 @@
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641680" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1566641680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566642007" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="EqualCheck.vhd"/>
<outfile xil_pn:name="NaNCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesTest.vhd"/>
<outfile xil_pn:name="TypeCheck.vhd"/>
<outfile xil_pn:name="ZeroCheck.vhd"/>
</transform>
<transform xil_pn:end_ts="1566641747" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2553664997009849434" xil_pn:start_ts="1566641747">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8700953375414271688" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566641747" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4514528137675365326" xil_pn:start_ts="1566641747">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641680" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8552960292560004185" xil_pn:start_ts="1566641680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566642007" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="EqualCheck.vhd"/>
<outfile xil_pn:name="NaNCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesTest.vhd"/>
<outfile xil_pn:name="TypeCheck.vhd"/>
<outfile xil_pn:name="ZeroCheck.vhd"/>
</transform>
<transform xil_pn:end_ts="1566642009" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="5476011783414369773" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesTest_beh.prj"/>
<outfile xil_pn:name="SpecialCasesTest_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1566642009" xil_pn:in_ck="-7882590952032427895" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8388436521910439718" xil_pn:start_ts="1566642009">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesTest_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="4779560239316253549" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-135021957620618676" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1647368633314702702" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8552960292560004185" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566062385" xil_pn:in_ck="-3915287225243783751" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566062357">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="6075245583379680512" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7265458583967929315" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641654" xil_pn:in_ck="7192749262906653965" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesCheck.lso"/>
<outfile xil_pn:name="SpecialCasesCheck.ngc"/>
<outfile xil_pn:name="SpecialCasesCheck.ngr"/>
@@ -122,35 +236,57 @@
<outfile xil_pn:name="SpecialCasesCheck.stx"/>
<outfile xil_pn:name="SpecialCasesCheck.syr"/>
<outfile xil_pn:name="SpecialCasesCheck.xst"/>
<outfile xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
<outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
<outfile xil_pn:name="TypeCheck.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1566062226" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566062226">
<transform xil_pn:end_ts="1566641654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566641654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1566641658" xil_pn:in_ck="-4436930658892351530" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1077053878783850095" xil_pn:start_ts="1566641654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="TypeCheck.bld"/>
<outfile xil_pn:name="TypeCheck.ngd"/>
<outfile xil_pn:name="TypeCheck_ngdbuild.xrpt"/>
<outfile xil_pn:name="SpecialCasesCheck.bld"/>
<outfile xil_pn:name="SpecialCasesCheck.ngd"/>
<outfile xil_pn:name="SpecialCasesCheck_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1566052863" xil_pn:in_ck="-1179315243053685469" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1566052862">
<transform xil_pn:end_ts="1566641665" xil_pn:in_ck="-238049757476689252" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="6289270943427689258" xil_pn:start_ts="1566641658">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="TypeCheck.twr"/>
<outfile xil_pn:name="TypeCheck.twx"/>
<outfile xil_pn:name="SpecialCasesCheck.pcf"/>
<outfile xil_pn:name="SpecialCasesCheck_map.map"/>
<outfile xil_pn:name="SpecialCasesCheck_map.mrp"/>
<outfile xil_pn:name="SpecialCasesCheck_map.ncd"/>
<outfile xil_pn:name="SpecialCasesCheck_map.ngm"/>
<outfile xil_pn:name="SpecialCasesCheck_map.xrpt"/>
<outfile xil_pn:name="SpecialCasesCheck_summary.xml"/>
<outfile xil_pn:name="SpecialCasesCheck_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1566641674" xil_pn:in_ck="7133440223257255534" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7367957561374022844" xil_pn:start_ts="1566641665">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SpecialCasesCheck.ncd"/>
<outfile xil_pn:name="SpecialCasesCheck.pad"/>
<outfile xil_pn:name="SpecialCasesCheck.par"/>
<outfile xil_pn:name="SpecialCasesCheck.ptwx"/>
<outfile xil_pn:name="SpecialCasesCheck.unroutes"/>
<outfile xil_pn:name="SpecialCasesCheck.xpi"/>
<outfile xil_pn:name="SpecialCasesCheck_pad.csv"/>
<outfile xil_pn:name="SpecialCasesCheck_pad.txt"/>
<outfile xil_pn:name="SpecialCasesCheck_par.xrpt"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1566641674" xil_pn:in_ck="2452388148884157204" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1566641670">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SpecialCasesCheck.twr"/>
<outfile xil_pn:name="SpecialCasesCheck.twx"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
</transform>
</transforms>

33
IEEE754Adder.xise
View File

@@ -16,17 +16,31 @@
<files>
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
</file>
</files>
<properties>
@@ -41,7 +55,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -83,7 +97,7 @@
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -284,7 +298,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -303,7 +318,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -358,7 +373,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SpecialCasesTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

BIN
NaNCheck_isim_beh.exe Executable file
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Binary file not shown.

2
NaNCheck_stx_beh.prj Normal file
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@@ -0,0 +1,2 @@
vhdl isim_temp "TypeCheck.vhd"
vhdl isim_temp "NaNCheck.vhd"

135
SpecialCasesCheck.bgn Normal file
View File

@@ -0,0 +1,135 @@
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6slx4.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225,
speed -3
Opened constraints file SpecialCasesCheck.pcf.
Sat Aug 24 10:52:28 2019
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g Encrypt:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 SpecialCasesCheck.ncd
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Not Specified)* |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No** |
+----------------------+----------------------+
| ConfigRate | 2** |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| LCK_cycle | NoWait** |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | Yes |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| Encrypt | No** |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| drive_awake | No** |
+----------------------+----------------------+
| Reset_on_err | No** |
+----------------------+----------------------+
| suspend_filter | Yes* |
+----------------------+----------------------+
| en_sw_gsr | No** |
+----------------------+----------------------+
| en_suspend | No* |
+----------------------+----------------------+
| sw_clk | Startupclk** |
+----------------------+----------------------+
| sw_gwe_cycle | 5** |
+----------------------+----------------------+
| sw_gts_cycle | 4** |
+----------------------+----------------------+
| multipin_wakeup | No** |
+----------------------+----------------------+
| wakeup_mask | 0x00* |
+----------------------+----------------------+
| ExtMasterCclk_en | No** |
+----------------------+----------------------+
| ExtMasterCclk_divide | 1* |
+----------------------+----------------------+
| CrcCoverage | No* |
+----------------------+----------------------+
| glutmask | Yes* |
+----------------------+----------------------+
| next_config_addr | 0x00000000* |
+----------------------+----------------------+
| next_config_new_mode | No* |
+----------------------+----------------------+
| next_config_boot_mode | 001* |
+----------------------+----------------------+
| next_config_register_write | Enable* |
+----------------------+----------------------+
| next_config_reboot | Enable* |
+----------------------+----------------------+
| golden_config_addr | 0x00000000* |
+----------------------+----------------------+
| failsafe_user | 0x0000* |
+----------------------+----------------------+
| TIMER_CFG | 0xFFFF |
+----------------------+----------------------+
| spi_buswidth | 1** |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | No** |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from SpecialCasesCheck.pcf.
Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "SpecialCasesCheck.bit".
Bitstream generation is complete.

BIN
SpecialCasesCheck.bit Normal file
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35
SpecialCasesCheck.bld Normal file
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@@ -0,0 +1,35 @@
Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc
SpecialCasesCheck.ngd
Reading NGO file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" ...
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 494556 kilobytes
Writing NGD file "SpecialCasesCheck.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "SpecialCasesCheck.bld"...

30
SpecialCasesCheck.cmd_log
View File

@@ -8,3 +8,33 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc SpecialCasesCheck.ngd
map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd SpecialCasesCheck.ncd SpecialCasesCheck.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o SpecialCasesCheck.twr SpecialCasesCheck.pcf
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc SpecialCasesCheck.ngd
map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd SpecialCasesCheck.ncd SpecialCasesCheck.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o SpecialCasesCheck.twr SpecialCasesCheck.pcf
bitgen -intstyle ise -f SpecialCasesCheck.ut SpecialCasesCheck.ncd
netgen -intstyle ise -ar Structure -tm SpecialCasesCheck -w -dir netgen/synthesis -ofmt vhdl -sim SpecialCasesCheck.ngc SpecialCasesCheck_synthesis.vhd
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc SpecialCasesCheck.ngd
map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd SpecialCasesCheck.ncd SpecialCasesCheck.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o SpecialCasesCheck.twr SpecialCasesCheck.pcf
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc SpecialCasesCheck.ngd
map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd SpecialCasesCheck.ncd SpecialCasesCheck.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o SpecialCasesCheck.twr SpecialCasesCheck.pcf
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xa6slx4-csg225-3 SpecialCasesCheck.ngc SpecialCasesCheck.ngd
map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd SpecialCasesCheck.pcf
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd SpecialCasesCheck.ncd SpecialCasesCheck.pcf
trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o SpecialCasesCheck.twr SpecialCasesCheck.pcf

8
SpecialCasesCheck.drc Normal file
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@@ -0,0 +1,8 @@
Release 14.7 Drc P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 24 10:52:28 2019
drc -z SpecialCasesCheck.ncd SpecialCasesCheck.pcf
DRC detected 0 errors and 0 warnings.

3
SpecialCasesCheck.ncd Normal file
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File diff suppressed because one or more lines are too long

2
SpecialCasesCheck.ngc
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File diff suppressed because one or more lines are too long

3
SpecialCasesCheck.ngd Normal file
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File diff suppressed because one or more lines are too long

2
SpecialCasesCheck.ngr
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255
SpecialCasesCheck.pad Normal file
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@@ -0,0 +1,255 @@
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 24 12:14:30 2019
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: SpecialCasesCheck_map.ncd
OUTPUT FILE: SpecialCasesCheck.pad
PART TYPE: xa6slx4
SPEED GRADE: -3
PACKAGE: csg225
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
A1|||GND||||||||||||
A2|Y<0>|IOB|IO_L1N_VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A3|Y<2>|IOB|IO_L2N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A4|Y<6>|IOB|IO_L4N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A5|Y<8>|IOB|IO_L6N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A6|Y<10>|IOB|IO_L33N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A7|Y<14>|IOB|IO_L35N_GCLK16_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A8|Y<16>|IOB|IO_L36N_GCLK14_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A9|Y<18>|IOB|IO_L37N_GCLK12_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A10|Y<24>|IOB|IO_L62N_VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A11|Y<26>|IOB|IO_L63N_SCP6_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A12|isZero|IOB|IO_L66N_SCP0_0|OUTPUT|LVCMOS25*|0|12|SLOW||||UNLOCATED|NO|NONE|
A13|Y<30>|IOB|IO_L65N_SCP2_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
A14|||TCK||||||||||||
A15|||GND||||||||||||
B1|||VCCAUX||||||||2.5||||
B2|isNaN|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS25*|0|12|SLOW||||UNLOCATED|NO|NONE|
B3|Y<1>|IOB|IO_L2P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B4|||VCCO_0|||0|||||2.50||||
B5|Y<9>|IOB|IO_L6P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B6|||GND||||||||||||
B7|Y<13>|IOB|IO_L35P_GCLK17_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B8|||VCCO_0|||0|||||2.50||||
B9|Y<17>|IOB|IO_L37P_GCLK13_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B10|||GND||||||||||||
B11|Y<25>|IOB|IO_L63P_SCP7_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B12|||VCCO_0|||0|||||2.50||||
B13|Y<29>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
B14||IOBM|IO_L1P_1|UNUSED||1|||||||||
B15||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
C1|X<31>|IOB|IO_L83N_VREF_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
C2|X<30>|IOB|IO_L83P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
C3|||GND||||||||||||
C4|Y<5>|IOB|IO_L4P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C5|Y<4>|IOB|IO_L3N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C6|Y<7>|IOB|IO_L33P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C7|||NC||||||||||||
C8|Y<15>|IOB|IO_L36P_GCLK15_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C9|Y<20>|IOB|IO_L39N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C10|Y<23>|IOB|IO_L62P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C11|Y<28>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C12|Y<31>|IOB|IO_L66P_SCP1_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
C13|||GND||||||||||||
C14||IOBM|IO_L33P_1|UNUSED||1|||||||||
C15||IOBS|IO_L33N_1|UNUSED||1|||||||||
D1|X<29>|IOB|IO_L54N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
D2|||VCCO_3|||3|||||any******||||
D3|X<28>|IOB|IO_L54P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
D4|X<26>|IOB|IO_L53P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
D5|Y<3>|IOB|IO_L3P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
D6|||NC||||||||||||
D7|||NC||||||||||||
D8|Y<12>|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
D9|||VCCO_0|||0|||||2.50||||
D10|Y<19>|IOB|IO_L39P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
D11|Y<27>|IOB|IO_L64P_SCP5_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
D12|||TDO||||||||||||
D13||IOBM|IO_L35P_1|UNUSED||1|||||||||
D14|||VCCO_1|||1|||||any******||||
D15||IOBS|IO_L35N_1|UNUSED||1|||||||||
E1|X<25>|IOB|IO_L52N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
E2|X<24>|IOB|IO_L52P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
E3|X<27>|IOB|IO_L53N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
E4|||NC||||||||||||
E5|||NC||||||||||||
E6|||NC||||||||||||
E7|Y<11>|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
E8|||NC||||||||||||
E9|Y<22>|IOB|IO_L40N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
E10|||TDI||||||||||||
E11|||GND||||||||||||
E12|||VCCAUX||||||||2.5||||
E13|||TMS||||||||||||
E14||IOBM|IO_L37P_1|UNUSED||1|||||||||
E15||IOBS|IO_L37N_1|UNUSED||1|||||||||
F1|X<23>|IOB|IO_L46N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
F2|||GND||||||||||||
F3|X<22>|IOB|IO_L46P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
F4|||NC||||||||||||
F5|||NC||||||||||||
F6|||GND||||||||||||
F7|||VCCAUX||||||||2.5||||
F8|||NC||||||||||||
F9|||VCCINT||||||||1.2||||
F10|Y<21>|IOB|IO_L40P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
F11|||NC||||||||||||
F12|||NC||||||||||||
F13||IOBM|IO_L39P_1|UNUSED||1|||||||||
F14|||GND||||||||||||
F15||IOBS|IO_L39N_1|UNUSED||1|||||||||
G1|X<12>|IOB|IO_L44N_GCLK20_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
G2|X<15>|IOB|IO_L44P_GCLK21_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
G3|||NC||||||||||||
G4|||VCCO_3|||3|||||any******||||
G5|||NC||||||||||||
G6|||VCCINT||||||||1.2||||
G7|||GND||||||||||||
G8|||VCCINT||||||||1.2||||
G9|||GND||||||||||||
G10|||VCCAUX||||||||2.5||||
G11|||NC||||||||||||
G12|||NC||||||||||||
G13|||NC||||||||||||
G14||IOBM|IO_L41P_GCLK9_IRDY1_1|UNUSED||1|||||||||
G15||IOBS|IO_L41N_GCLK8_1|UNUSED||1|||||||||
H1|X<18>|IOB|IO_L42N_GCLK24_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
H2|||VCCO_3|||3|||||any******||||
H3|X<14>|IOB|IO_L42P_GCLK25_TRDY2_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
H4|||NC||||||||||||
H5|||NC||||||||||||
H6|||NC||||||||||||
H7|||VCCINT||||||||1.2||||
H8|||GND||||||||||||
H9|||VCCINT||||||||1.2||||
H10|||NC||||||||||||
H11|||NC||||||||||||
H12|||NC||||||||||||
H13||IOBM|IO_L42P_GCLK7_1|UNUSED||1|||||||||
H14|||VCCO_1|||1|||||any******||||
H15||IOBS|IO_L42N_GCLK6_TRDY1_1|UNUSED||1|||||||||
J1|X<16>|IOB|IO_L41N_GCLK26_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
J2|X<19>|IOB|IO_L41P_GCLK27_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
J3|X<17>|IOB|IO_L43N_GCLK22_IRDY2_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
J4|X<21>|IOB|IO_L45N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
J5|||NC||||||||||||
J6|||VCCAUX||||||||2.5||||
J7|||GND||||||||||||
J8|||VCCINT||||||||1.2||||
J9|||GND||||||||||||
J10|||VCCINT||||||||1.2||||
J11||IOBM|IO_L36P_1|UNUSED||1|||||||||
J12|||VCCO_1|||1|||||any******||||
J13||IOBS|IO_L36N_1|UNUSED||1|||||||||
J14||IOBM|IO_L43P_GCLK5_1|UNUSED||1|||||||||
J15||IOBS|IO_L43N_GCLK4_1|UNUSED||1|||||||||
K1|X<11>|IOB|IO_L40N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
K2|||GND||||||||||||
K3|X<10>|IOB|IO_L40P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
K4|X<20>|IOB|IO_L43P_GCLK23_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
K5|X<13>|IOB|IO_L45P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
K6|||GND||||||||||||
K7|||VCCINT||||||||1.2||||
K8||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
K9|||VCCAUX||||||||2.5||||
K10||IOBM|IO_L38P_1|UNUSED||1|||||||||
K11||IOBS|IO_L38N_1|UNUSED||1|||||||||
K12||IOBM|IO_L40P_GCLK11_1|UNUSED||1|||||||||
K13||IOBM|IO_L44P_1|UNUSED||1|||||||||
K14|||GND||||||||||||
K15||IOBS|IO_L44N_1|UNUSED||1|||||||||
L1|X<9>|IOB|IO_L39N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
L2|X<8>|IOB|IO_L39P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
L3|X<5>|IOB|IO_L1N_VREF_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
L4|||VCCAUX||||||||2.5||||
L5||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
L6||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
L7|||NC||||||||||||
L8||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
L9||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
L10|||CMPCS_B_2||||||||||||
L11|||GND||||||||||||
L12||IOBS|IO_L40N_GCLK10_1|UNUSED||1|||||||||
L13|||SUSPEND||||||||||||
L14||IOBM|IO_L45P_1|UNUSED||1|||||||||
L15||IOBS|IO_L45N_1|UNUSED||1|||||||||
M1|X<1>|IOB|IO_L38N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
M2|||VCCO_3|||3|||||any******||||
M3|X<0>|IOB|IO_L38P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
M4|X<4>|IOB|IO_L1P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
M5||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
M6|||NC||||||||||||
M7|||VCCO_2|||2|||||any******||||
M8||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
M9|||NC||||||||||||
M10||IOBS|IO_L14N_D12_2|UNUSED||2|||||||||
M11||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
M12|||VCCAUX||||||||2.5||||
M13||IOBM|IO_L46P_1|UNUSED||1|||||||||
M14|||VCCO_1|||1|||||any******||||
M15||IOBS|IO_L46N_1|UNUSED||1|||||||||
N1|X<7>|IOB|IO_L37N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
N2|X<6>|IOB|IO_L37P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
N3|||GND||||||||||||
N4||IOBM|IO_L63P_2|UNUSED||2|||||||||
N5||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
N6||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
N7||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
N8||IOBM|IO_L29P_GCLK3_2|UNUSED||2|||||||||
N9|||NC||||||||||||
N10||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
N11||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
N12||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
N13|||GND||||||||||||
N14||IOBM|IO_L47P_1|UNUSED||1|||||||||
N15||IOBS|IO_L47N_1|UNUSED||1|||||||||
P1|X<3>|IOB|IO_L2N_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
P2|X<2>|IOB|IO_L2P_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
P3||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
P4|||VCCO_2|||2|||||any******||||
P5||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
P6|||GND||||||||||||
P7||IOBM|IO_L32P_GCLK29_2|UNUSED||2|||||||||
P8|||VCCO_2|||2|||||any******||||
P9||IOBM|IO_L16P_2|UNUSED||2|||||||||
P10|||GND||||||||||||
P11||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
P12|||VCCO_2|||2|||||any******||||
P13||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
P14||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
P15||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
R1|||GND||||||||||||
R2|||PROGRAM_B_2||||||||||||
R3||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
R4||IOBS|IO_L63N_2|UNUSED||2|||||||||
R5||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
R6||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
R7||IOBS|IO_L32N_GCLK28_2|UNUSED||2|||||||||
R8||IOBS|IO_L29N_GCLK2_2|UNUSED||2|||||||||
R9||IOBS|IO_L16N_VREF_2|UNUSED||2|||||||||
R10||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
R11||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
R12||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
R13||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
R14|||DONE_2||||||||||||
R15|||GND||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

147
SpecialCasesCheck.par Normal file
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@@ -0,0 +1,147 @@
Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Xilinx:: Sat Aug 24 12:14:27 2019
par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd
SpecialCasesCheck.ncd SpecialCasesCheck.pcf
Constraints file: SpecialCasesCheck.pcf.
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
Initializing temperature to 100.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 0 out of 4,800 0%
Number of Slice LUTs: 26 out of 2,400 1%
Number used as logic: 26 out of 2,400 1%
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 0 out of 1,200 0%
Slice Logic Distribution:
Number of occupied Slices: 10 out of 600 1%
Number of MUXCYs used: 12 out of 1,200 1%
Number of LUT Flip Flop pairs used: 26
Number with an unused Flip Flop: 26 out of 26 100%
Number with an unused LUT: 0 out of 26 0%
Number of fully used LUT-FF pairs: 0 out of 26 0%
Number of slice register sites lost
to control set restrictions: 0 out of 4,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 132 50%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 12 0%
Number of RAMB8BWERs: 0 out of 24 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 8 0%
Number of ICAPs: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs
Starting Router
Phase 1 : 155 unrouted; REAL time: 2 secs
Phase 2 : 145 unrouted; REAL time: 2 secs
Phase 3 : 214 unrouted; REAL time: 2 secs
Phase 4 : 214 unrouted; (Par is working to improve performance) REAL time: 2 secs
Updating file: SpecialCasesCheck.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
Total REAL time to Router completion: 3 secs
Total CPU time to Router completion: 3 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 3 secs
Total CPU time to PAR completion: 3 secs
Peak Memory Usage: 596 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2
Writing design to file SpecialCasesCheck.ncd
PAR done!

4
SpecialCasesCheck.pcf Normal file
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@@ -0,0 +1,4 @@
//! **************************************************************************
// Written by: Map P.20131013 on Sat Aug 24 12:14:25 2019
//! **************************************************************************

2
SpecialCasesCheck.prj
View File

@@ -1,3 +1,5 @@
vhdl work "TypeCheck.vhd"
vhdl work "EqualCheck.vhd"
vhdl work "ZeroCheck.vhd"
vhdl work "NaNCheck.vhd"
vhdl work "SpecialCasesCheck.vhd"

332
SpecialCasesCheck.ptwx Normal file
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@@ -0,0 +1,332 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt></twSumRpt></twBody></twReport>

99
SpecialCasesCheck.syr
View File

@@ -1,18 +1,18 @@
Release 14.7 - xst P.20160913 (lin64)
Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.05 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
Total CPU time to Xst completion: 0.05 secs
-->
Reading design: SpecialCasesCheck.prj
@@ -108,13 +108,19 @@ Slice Utilization Ratio Delta : 5
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work
Parsing entity <TypeCheck>.
Parsing architecture <TypeCheckArch> of entity <typecheck>.
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work
Parsing entity <EqualCheck>.
Parsing architecture <EqualCheckArch> of entity <equalcheck>.
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
Parsing entity <ZeroCheck>.
Parsing architecture <ZeroCheckArch> of entity <zerocheck>.
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
Parsing entity <NaNCheck>.
Parsing architecture <NaNCheckArch> of entity <nancheck>.
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
Parsing entity <SpecialCasesCheck>.
Parsing architecture <SpecialCasesCheckArch> of entity <specialcasescheck>.
@@ -128,33 +134,52 @@ Elaborating entity <NaNCheck> (architecture <NaNCheckArch>) from library <work>.
Elaborating entity <TypeCheck> (architecture <TypeCheckArch>) from library <work>.
Elaborating entity <ZeroCheck> (architecture <ZeroCheckArch>) from library <work>.
Elaborating entity <EqualCheck> (architecture <EqualCheckArch>) with generics from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <SpecialCasesCheck>.
Related source file is "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd".
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
Summary:
no macro.
Unit <SpecialCasesCheck> synthesized.
Synthesizing Unit <NaNCheck>.
Related source file is "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd".
Related source file is "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd".
Summary:
no macro.
Unit <NaNCheck> synthesized.
Synthesizing Unit <TypeCheck>.
Related source file is "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd".
Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
WARNING:Xst:647 - Input <N<31:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <TypeCheck> synthesized.
Synthesizing Unit <ZeroCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd".
Summary:
Unit <ZeroCheck> synthesized.
Synthesizing Unit <EqualCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd".
BITCOUNT = 31
Summary:
Unit <EqualCheck> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
Macro Statistics
# Xors : 2
1-bit xor2 : 1
31-bit xor2 : 1
=========================================================================
=========================================================================
@@ -165,7 +190,11 @@ Found no macro
=========================================================================
Advanced HDL Synthesis Report
Found no macro
Macro Statistics
# Xors : 2
1-bit xor2 : 1
31-bit xor2 : 1
=========================================================================
=========================================================================
@@ -176,7 +205,7 @@ Optimizing unit <SpecialCasesCheck> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 0.
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
Final Macro Processing ...
@@ -205,12 +234,14 @@ Top Level Output File Name : SpecialCasesCheck.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 16
# BELS : 39
# GND : 1
# LUT3 : 2
# LUT4 : 2
# LUT4 : 3
# LUT5 : 2
# LUT6 : 9
# LUT6 : 19
# MUXCY : 11
# VCC : 1
# IO Buffers : 66
# IBUF : 64
# OBUF : 2
@@ -222,14 +253,14 @@ Selected Device : xa6slx4csg225-3
Slice Logic Utilization:
Number of Slice LUTs: 15 out of 2400 0%
Number used as Logic: 15 out of 2400 0%
Number of Slice LUTs: 26 out of 2400 1%
Number used as Logic: 26 out of 2400 1%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 15
Number with an unused Flip Flop: 15 out of 15 100%
Number with an unused LUT: 0 out of 15 0%
Number of fully used LUT-FF pairs: 0 out of 15 0%
Number of LUT Flip Flop pairs used: 26
Number with an unused Flip Flop: 26 out of 26 100%
Number with an unused LUT: 0 out of 26 0%
Number of fully used LUT-FF pairs: 0 out of 26 0%
Number of unique control sets: 0
IO Utilization:
@@ -269,7 +300,7 @@ Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.532ns
Maximum combinational path delay: 7.570ns
Timing Details:
---------------
@@ -277,24 +308,24 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 64 / 1
Total number of paths / destination ports: 128 / 2
-------------------------------------------------------------------------
Delay: 7.532ns (Levels of Logic = 5)
Delay: 7.570ns (Levels of Logic = 5)
Source: Y<4> (PAD)
Destination: isNan (PAD)
Destination: isNaN (PAD)
Data Path: Y<4> to isNan
Data Path: Y<4> to isNaN
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.944 Y_4_IBUF (Y_4_IBUF)
IBUF:I->O 2 1.222 0.981 Y_4_IBUF (Y_4_IBUF)
LUT6:I0->O 1 0.203 0.924 NC/isNan11 (NC/isNan10)
LUT6:I1->O 1 0.203 0.684 NC/isNan12 (NC/isNan11)
LUT6:I4->O 1 0.203 0.579 NC/isNan13 (isNan_OBUF)
OBUF:I->O 2.571 isNan_OBUF (isNan)
LUT6:I4->O 1 0.203 0.579 NC/isNan13 (isNaN_OBUF)
OBUF:I->O 2.571 isNaN_OBUF (isNaN)
----------------------------------------
Total 7.532ns (4.402ns logic, 3.130ns route)
(58.4% logic, 41.6% route)
Total 7.570ns (4.402ns logic, 3.168ns route)
(58.2% logic, 41.8% route)
=========================================================================
@@ -304,13 +335,13 @@ Cross Clock Domains Report:
=========================================================================
Total REAL time to Xst completion: 22.00 secs
Total CPU time to Xst completion: 19.75 secs
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.87 secs
-->
Total memory usage is 473740 kilobytes
Total memory usage is 474696 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)

180
SpecialCasesCheck.twr Normal file
View File

@@ -0,0 +1,180 @@
--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml SpecialCasesCheck.twx SpecialCasesCheck.ncd -o
SpecialCasesCheck.twr SpecialCasesCheck.pcf
Design file: SpecialCasesCheck.ncd
Physical constraint file: SpecialCasesCheck.pcf
Device,package,speed: xa6slx4,csg225,I,-3 (PRODUCTION 1.23 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
X<0> |isNaN | 11.058|
X<0> |isZero | 10.439|
X<1> |isNaN | 10.377|
X<1> |isZero | 10.430|
X<2> |isNaN | 11.612|
X<2> |isZero | 11.959|
X<3> |isNaN | 11.649|
X<3> |isZero | 12.050|
X<4> |isNaN | 11.411|
X<4> |isZero | 12.228|
X<5> |isNaN | 11.466|
X<5> |isZero | 12.267|
X<6> |isNaN | 11.193|
X<6> |isZero | 10.961|
X<7> |isNaN | 10.751|
X<7> |isZero | 10.961|
X<8> |isNaN | 10.537|
X<8> |isZero | 10.199|
X<9> |isNaN | 10.777|
X<9> |isZero | 10.575|
X<10> |isNaN | 10.437|
X<10> |isZero | 10.602|
X<11> |isNaN | 10.209|
X<11> |isZero | 10.255|
X<12> |isNaN | 10.593|
X<12> |isZero | 10.323|
X<13> |isNaN | 11.004|
X<13> |isZero | 10.164|
X<14> |isNaN | 9.715|
X<14> |isZero | 10.438|
X<15> |isNaN | 9.739|
X<15> |isZero | 10.549|
X<16> |isNaN | 10.397|
X<16> |isZero | 10.155|
X<17> |isNaN | 10.558|
X<17> |isZero | 10.611|
X<18> |isNaN | 10.474|
X<18> |isZero | 10.178|
X<19> |isNaN | 10.628|
X<19> |isZero | 10.520|
X<20> |isNaN | 10.053|
X<20> |isZero | 9.886|
X<21> |isNaN | 10.305|
X<21> |isZero | 10.507|
X<22> |isNaN | 10.517|
X<22> |isZero | 10.336|
X<23> |isNaN | 10.601|
X<23> |isZero | 10.255|
X<24> |isNaN | 11.962|
X<24> |isZero | 11.311|
X<25> |isNaN | 12.771|
X<25> |isZero | 11.767|
X<26> |isNaN | 12.691|
X<26> |isZero | 11.904|
X<27> |isNaN | 11.589|
X<27> |isZero | 11.480|
X<28> |isNaN | 12.509|
X<28> |isZero | 11.705|
X<29> |isNaN | 12.376|
X<29> |isZero | 11.985|
X<30> |isNaN | 11.605|
X<30> |isZero | 12.031|
X<31> |isNaN | 11.600|
X<31> |isZero | 12.093|
Y<0> |isNaN | 12.007|
Y<0> |isZero | 11.318|
Y<1> |isNaN | 12.520|
Y<1> |isZero | 11.716|
Y<2> |isNaN | 12.380|
Y<2> |isZero | 11.204|
Y<3> |isNaN | 13.232|
Y<3> |isZero | 12.157|
Y<4> |isNaN | 12.840|
Y<4> |isZero | 12.195|
Y<5> |isNaN | 12.972|
Y<5> |isZero | 11.995|
Y<6> |isNaN | 12.862|
Y<6> |isZero | 11.584|
Y<7> |isNaN | 12.444|
Y<7> |isZero | 11.999|
Y<8> |isNaN | 11.471|
Y<8> |isZero | 10.830|
Y<9> |isNaN | 12.280|
Y<9> |isZero | 11.614|
Y<10> |isNaN | 12.134|
Y<10> |isZero | 11.822|
Y<11> |isNaN | 12.422|
Y<11> |isZero | 11.258|
Y<12> |isNaN | 12.756|
Y<12> |isZero | 12.304|
Y<13> |isNaN | 12.566|
Y<13> |isZero | 11.665|
Y<14> |isNaN | 12.155|
Y<14> |isZero | 12.355|
Y<15> |isNaN | 12.706|
Y<15> |isZero | 12.350|
Y<16> |isNaN | 11.995|
Y<16> |isZero | 12.040|
Y<17> |isNaN | 12.800|
Y<17> |isZero | 11.894|
Y<18> |isNaN | 12.487|
Y<18> |isZero | 11.659|
Y<19> |isNaN | 13.125|
Y<19> |isZero | 12.410|
Y<20> |isNaN | 12.779|
Y<20> |isZero | 12.344|
Y<21> |isNaN | 12.140|
Y<21> |isZero | 12.176|
Y<22> |isNaN | 13.510|
Y<22> |isZero | 12.862|
Y<23> |isNaN | 12.305|
Y<23> |isZero | 11.548|
Y<24> |isNaN | 12.209|
Y<24> |isZero | 12.461|
Y<25> |isNaN | 12.196|
Y<25> |isZero | 12.322|
Y<26> |isNaN | 12.417|
Y<26> |isZero | 12.754|
Y<27> |isNaN | 12.064|
Y<27> |isZero | 12.007|
Y<28> |isNaN | 11.833|
Y<28> |isZero | 11.870|
Y<29> |isNaN | 12.434|
Y<29> |isZero | 12.705|
Y<30> |isNaN | 11.894|
Y<30> |isZero | 12.131|
Y<31> |isNaN | 11.196|
Y<31> |isZero | 11.621|
---------------+---------------+---------+
Analysis completed Sat Aug 24 12:14:33 2019
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 374 MB

339
SpecialCasesCheck.twx Normal file
View File

File diff suppressed because one or more lines are too long

9
SpecialCasesCheck.unroutes Normal file
View File

@@ -0,0 +1,9 @@
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 24 12:14:30 2019
All signals are completely routed.

31
SpecialCasesCheck.ut Normal file
View File

@@ -0,0 +1,31 @@
-w
-g DebugBitstream:No
-g Binary:no
-g CRC:Enable
-g Reset_on_err:No
-g ConfigRate:2
-g ProgPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullUp
-g TmsPin:PullUp
-g UnusedPin:PullDown
-g UserID:0xFFFFFFFF
-g ExtMasterCclk_en:No
-g SPI_buswidth:1
-g TIMER_CFG:0xFFFF
-g multipin_wakeup:No
-g StartUpClk:CClk
-g DONE_cycle:4
-g GTS_cycle:5
-g GWE_cycle:6
-g LCK_cycle:NoWait
-g Security:None
-g DonePipe:Yes
-g DriveDone:No
-g Encrypt:No
-g en_sw_gsr:No
-g drive_awake:No
-g sw_clk:Startupclk
-g sw_gwe_cycle:5
-g sw_gts_cycle:4

25
SpecialCasesCheck.vhd
View File

@@ -4,7 +4,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity SpecialCasesCheck is
port(
X, Y: in std_logic_vector(31 downto 0);
isNan, isZero: out std_logic
isNaN, isZero: out std_logic
);
end SpecialCasesCheck;
@@ -13,24 +13,21 @@ architecture SpecialCasesCheckArch of SpecialCasesCheck is
component NaNCheck is
port(
X, Y: in std_logic_vector(31 downto 0);
isNan: out std_logic
isNaN: out std_logic
);
end component;
signal xSign: std_logic;
signal ySign: std_logic;
signal isSameAbsValue: std_logic;
component ZeroCheck is
port(
X, Y: in std_logic_vector(31 downto 0);
isZero: out std_logic
);
end component;
begin
NC: NaNCheck
port map (X => X, Y => Y, isNan => isNan);
xSign <= X(31);
ySign <= Y(31);
isSameAbsValue <= '0'; -- TODO
isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue);
port map (X => X, Y => Y, isNaN => isNaN);
ZC: ZeroCheck
port map (X => X, Y => Y, isZero => isZero);
end SpecialCasesCheckArch;

3
SpecialCasesCheck.xpi Normal file
View File

@@ -0,0 +1,3 @@
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF

8
SpecialCasesCheck_bitgen.xwbt Normal file
View File

@@ -0,0 +1,8 @@
INTSTYLE=ise
INFILE=/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
OUTFILE=/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.bit
FAMILY=Automotive Spartan6
PART=xa6slx4-3csg225
WORKINGDIR=/home/Luca/ISE/IEEE754Adder
LICENSE=WebPack
USER_INFO=211697841_0_0_919

223
SpecialCasesCheck_envsettings.html
View File

@@ -15,52 +15,45 @@
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>LMC_HOME</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
</tr>
<tr>
<td>PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/ise/bin</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
</tr>
<tr>
<td>XILINX</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
@@ -351,6 +344,150 @@
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xa6slx4-csg225-3</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>high</td>
</tr>
<tr>
<td>-xt</td>
<td>Extra Cost Tables</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-t</td>
<td>Starting Placer Cost Table (1-100) Map</td>
<td>1</td>
<td>0</td>
</tr>
<tr>
<td>-r</td>
<td>Register Ordering</td>
<td>4</td>
<td>4</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-lc</td>
<td>LUT Combining</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-o</td>
<td>&nbsp;</td>
<td>SpecialCasesCheck_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xa6slx4-csg225-3</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-mt</td>
<td>Enable Multi-Threading</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
@@ -365,31 +502,31 @@
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>localhost.localdomain</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td>Xilinx</td>
<td>Xilinx</td>
<td>Xilinx</td>
<td>Xilinx</td>
</tr>
<tr>
<td>OS Name</td>
<td>OracleServer</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td>CentOS</td>
<td>CentOS</td>
<td>CentOS</td>
<td>CentOS</td>
</tr>
<tr>
<td>OS Release</td>
<td>Oracle Linux Server release 6.4</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td>CentOS release 6.10 (Final)</td>
<td>CentOS release 6.10 (Final)</td>
<td>CentOS release 6.10 (Final)</td>
<td>CentOS release 6.10 (Final)</td>
</tr>
</TABLE>
</BODY> </HTML>

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Release 14.7 Map P.20131013 (lin64)
Xilinx Map Application Log File for Design 'SpecialCasesCheck'
Design Information
------------------
Command Line : map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd
SpecialCasesCheck.pcf
Target Device : xa6slx4
Target Package : csg225
Target Speed : -3
Mapper Version : aspartan6 -- $Revision: 1.55 $
Mapped Date : Sat Aug 24 12:14:20 2019
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 3 secs
Total CPU time at the beginning of Placer: 3 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1afc) REAL time: 3 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1afc) REAL time: 3 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:1afc) REAL time: 3 secs
Phase 4.2 Initial Placement for Architecture Specific Features
...
....
Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:1afc) REAL time: 4 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:1afc) REAL time: 4 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:1afc) REAL time: 4 secs
Phase 7.3 Local Placement Optimization
...
....
Phase 7.3 Local Placement Optimization (Checksum:789e990e) REAL time: 4 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:789e990e) REAL time: 4 secs
Phase 9.8 Global Placement
...................
.........................
Phase 9.8 Global Placement (Checksum:97cecb7e) REAL time: 4 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:97cecb7e) REAL time: 4 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:bebeaa60) REAL time: 4 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:bebeaa60) REAL time: 4 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:bebeaa60) REAL time: 4 secs
Total REAL time to Placer completion: 4 secs
Total CPU time to Placer completion: 4 secs
Running post-placement packing...
Writing output files...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 0 out of 4,800 0%
Number of Slice LUTs: 26 out of 2,400 1%
Number used as logic: 26 out of 2,400 1%
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 0 out of 1,200 0%
Slice Logic Distribution:
Number of occupied Slices: 10 out of 600 1%
Number of MUXCYs used: 12 out of 1,200 1%
Number of LUT Flip Flop pairs used: 26
Number with an unused Flip Flop: 26 out of 26 100%
Number with an unused LUT: 0 out of 26 0%
Number of fully used LUT-FF pairs: 0 out of 26 0%
Number of slice register sites lost
to control set restrictions: 0 out of 4,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 132 50%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 12 0%
Number of RAMB8BWERs: 0 out of 24 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 8 0%
Number of ICAPs: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.78
Peak Memory Usage: 734 MB
Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 5 secs
Mapping completed.
See MAP report file "SpecialCasesCheck_map.mrp" for details.

245
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@@ -0,0 +1,245 @@
Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'SpecialCasesCheck'
Design Information
------------------
Command Line : map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd
SpecialCasesCheck.pcf
Target Device : xa6slx4
Target Package : csg225
Target Speed : -3
Mapper Version : aspartan6 -- $Revision: 1.55 $
Mapped Date : Sat Aug 24 12:14:20 2019
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 0 out of 4,800 0%
Number of Slice LUTs: 26 out of 2,400 1%
Number used as logic: 26 out of 2,400 1%
Number using O6 output only: 25
Number using O5 output only: 0
Number using O5 and O6: 1
Number used as ROM: 0
Number used as Memory: 0 out of 1,200 0%
Slice Logic Distribution:
Number of occupied Slices: 10 out of 600 1%
Number of MUXCYs used: 12 out of 1,200 1%
Number of LUT Flip Flop pairs used: 26
Number with an unused Flip Flop: 26 out of 26 100%
Number with an unused LUT: 0 out of 26 0%
Number of fully used LUT-FF pairs: 0 out of 26 0%
Number of slice register sites lost
to control set restrictions: 0 out of 4,800 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 66 out of 132 50%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 12 0%
Number of RAMB8BWERs: 0 out of 24 0%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 0 out of 16 0%
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 8 0%
Number of ICAPs: 0 out of 1 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 1.78
Peak Memory Usage: 734 MB
Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 5 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 100.000 Celsius. (default - Range:
-40.000 to 100.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| X<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<8> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<9> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<10> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<11> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<12> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<13> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<14> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<15> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<16> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<17> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<18> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<19> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<20> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<21> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<22> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<23> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<24> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<25> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<26> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<27> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<28> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<29> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<30> | IOB | INPUT | LVCMOS25 | | | | | | |
| X<31> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<8> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<9> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<10> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<11> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<12> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<13> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<14> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<15> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<16> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<17> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<18> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<19> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<20> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<21> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<22> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<23> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<24> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<25> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<26> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<27> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<28> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<29> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<30> | IOB | INPUT | LVCMOS25 | | | | | | |
| Y<31> | IOB | INPUT | LVCMOS25 | | | | | | |
| isNaN | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| isZero | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.

3
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SpecialCasesCheck_map.ngm Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Sat Aug 24 12:14:25 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/Luca/bin"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="CentOS"/>
<item stringID="User_EnvOsrelease" value="CentOS release 6.10 (Final)"/>
</item>
<item stringID="User_EnvHost" value="Xilinx"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="2">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="3">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
</table>
</section>
<section stringID="MAP_OPTION_SUMMARY">
<item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
<item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
<item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
<item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
<item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
<item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
<item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="SpecialCasesCheck_map.ncd"/>
<item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xa6slx4-csg225-3"/>
</section>
<task stringID="MAP_PACK_REPORT">
<item AVAILABLE="4800" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="0">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="26">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="25"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="132" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
<item AVAILABLE="68" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="34" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
<item AVAILABLE="66" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
<item AVAILABLE="34" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
<item AVAILABLE="66" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
<section stringID="MAP_DESIGN_INFORMATION">
<item stringID="MAP_PART" value="xa6slx4csg225-3"/>
<item stringID="MAP_DEVICE" value="xa6slx4"/>
<item stringID="MAP_ARCHITECTURE" value="aspartan6"/>
<item stringID="MAP_PACKAGE" value="csg225"/>
<item stringID="MAP_SPEED" value="-3"/>
</section>
<section stringID="MAP_DESIGN_SUMMARY">
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="751136"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="5 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="5 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="4800" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="0">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="26">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="0"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="25"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="1"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_DPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_EXO5" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_O5ANDO6" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="600" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="10">
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_SLICEL" value="3"/>
<item AVAILABLE="300" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="300" dataType="int" stringID="MAP_NUM_SLICEX" value="7"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="26">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="26"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="0"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="0"/>
</item>
</section>
<section stringID="MAP_IOB_REPORTING">
<item AVAILABLE="132" dataType="int" stringID="MAP_AGG_BONDED_IO" value="66"/>
<item AVAILABLE="68" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
<item AVAILABLE="0" dataType="int" label="IOB Flip Flops" stringID="MAP_NUM_IOB_FF" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
<item AVAILABLE="34" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
<item AVAILABLE="66" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
<item AVAILABLE="34" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
<item AVAILABLE="66" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
</section>
<section stringID="MAP_HARD_IP_REPORTING"/>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="12" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="0"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
</section>
<section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
<section stringID="MAP_IOB_PROPERTIES">
<table stringID="MAP_IOB_TABLE">
<column label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME"/>
<column stringID="Type"/>
<column stringID="Direction"/>
<column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
<column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
<column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
<column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
<column label="Reg&#xA;(s)" stringID="REGS"/>
<column stringID="Resistor"/>
<column label="IOB&#xA;Delay" stringID="IOB_DELAY"/>
<row stringID="row" value="1">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="2">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="3">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="4">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="5">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="6">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;5>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="7">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="8">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="9">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;8>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="10">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;9>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="11">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;10>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="12">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;11>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="13">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;12>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="14">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;13>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="15">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;14>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="16">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;15>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="17">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;16>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="18">
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</row>
<row stringID="row" value="19">
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</row>
<row stringID="row" value="20">
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<item stringID="Type" value="IOB"/>
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</row>
<row stringID="row" value="21">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;20>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="22">
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<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="23">
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<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="24">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;23>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="25">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;24>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="26">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;25>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="27">
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<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="28">
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<item stringID="Type" value="IOB"/>
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</row>
<row stringID="row" value="29">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;28>"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="30">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;29>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="31">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;30>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="32">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="X&lt;31>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="33">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;0>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="34">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;1>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="35">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;2>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="36">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;3>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="37">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;4>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="38">
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<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="39">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;6>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="40">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;7>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="41">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;8>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="42">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;9>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="43">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;10>"/>
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<row stringID="row" value="44">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;11>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="45">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;12>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
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<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="47">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;14>"/>
<item stringID="Type" value="IOB"/>
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</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;15>"/>
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</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;16>"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;18>"/>
<item stringID="Type" value="IOB"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="52">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;19>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;21>"/>
<item stringID="Type" value="IOB"/>
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</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;22>"/>
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</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;23>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;24>"/>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;25>"/>
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<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="59">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;26>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
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<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;27>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="61">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;28>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="62">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;29>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="63">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;30>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="64">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="Y&lt;31>"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="INPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
</row>
<row stringID="row" value="65">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="isNaN"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
<row stringID="row" value="66">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="isZero"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
</row>
</table>
</section>
<section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="1"/>
</section>
</section>
<section stringID="MAP_GUIDE_REPORT"/>
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
<section stringID="MAP_TIMING_REPORT"/>
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
<section stringID="MAP_GENERAL_CONFIG_DATA"/>
<section stringID="MAP_CONTROL_SET_INFORMATION">
<item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="0"/>
<tree stringID="MAP_CONTROL_SET_HIERARCHY">
<property stringID="MAP_CLOCK_SIGNAL"/>
<property stringID="MAP_RESET_SIGNAL"/>
<property stringID="MAP_SET_SIGNAL"/>
<property stringID="MAP_ENABLE_SIGNAL"/>
<property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
<property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
</tree>
</section>
</task>
<section stringID="MAP_RAM_FIFO_DATA">
<item AVAILABLE="12" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="0"/>
<item AVAILABLE="24" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
</section>
<section stringID="MAP_IP_DATA">
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
<item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
<item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
<item AVAILABLE="8" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
<item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
<item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
<item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
</section>
<section stringID="MAP_BUFG_DATA">
<item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="0"/>
<item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
<item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
<item dataType="int" stringID="MAP_RPMS" value="0"/>
</section>
</application>
</document>

107
SpecialCasesCheck_ngdbuild.xrpt Normal file
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@@ -0,0 +1,107 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Aug 24 12:14:17 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/Luca/bin"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="CentOS"/>
<item stringID="User_EnvOsrelease" value="CentOS release 6.10 (Final)"/>
</item>
<item stringID="User_EnvHost" value="Xilinx"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="2">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="3">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xa6slx4-csg225-3"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="64"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="64"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="11"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>

256
SpecialCasesCheck_pad.csv Normal file
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@@ -0,0 +1,256 @@
#Release 14.7 - par P.20131013 (lin64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Sat Aug 24 12:14:30 2019
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: SpecialCasesCheck_map.ncd
#OUTPUT FILE: SpecialCasesCheck_pad.csv
#PART TYPE: xa6slx4
#SPEED GRADE: -3
#PACKAGE: csg225
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
A1,,,GND,,,,,,,,,,,,
A2,Y<0>,IOB,IO_L1N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A3,Y<2>,IOB,IO_L2N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A4,Y<6>,IOB,IO_L4N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A5,Y<8>,IOB,IO_L6N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A6,Y<10>,IOB,IO_L33N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A7,Y<14>,IOB,IO_L35N_GCLK16_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A8,Y<16>,IOB,IO_L36N_GCLK14_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A9,Y<18>,IOB,IO_L37N_GCLK12_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A10,Y<24>,IOB,IO_L62N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A11,Y<26>,IOB,IO_L63N_SCP6_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A12,isZero,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,UNLOCATED,NO,NONE,
A13,Y<30>,IOB,IO_L65N_SCP2_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
A14,,,TCK,,,,,,,,,,,,
A15,,,GND,,,,,,,,,,,,
B1,,,VCCAUX,,,,,,,,2.5,,,,
B2,isNaN,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,UNLOCATED,NO,NONE,
B3,Y<1>,IOB,IO_L2P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B4,,,VCCO_0,,,0,,,,,2.50,,,,
B5,Y<9>,IOB,IO_L6P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B6,,,GND,,,,,,,,,,,,
B7,Y<13>,IOB,IO_L35P_GCLK17_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B8,,,VCCO_0,,,0,,,,,2.50,,,,
B9,Y<17>,IOB,IO_L37P_GCLK13_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B10,,,GND,,,,,,,,,,,,
B11,Y<25>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B12,,,VCCO_0,,,0,,,,,2.50,,,,
B13,Y<29>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
B14,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,,
B15,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,,
C1,X<31>,IOB,IO_L83N_VREF_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
C2,X<30>,IOB,IO_L83P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
C3,,,GND,,,,,,,,,,,,
C4,Y<5>,IOB,IO_L4P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C5,Y<4>,IOB,IO_L3N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C6,Y<7>,IOB,IO_L33P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C7,,,NC,,,,,,,,,,,,
C8,Y<15>,IOB,IO_L36P_GCLK15_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C9,Y<20>,IOB,IO_L39N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C10,Y<23>,IOB,IO_L62P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C11,Y<28>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C12,Y<31>,IOB,IO_L66P_SCP1_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
C13,,,GND,,,,,,,,,,,,
C14,,IOBM,IO_L33P_1,UNUSED,,1,,,,,,,,,
C15,,IOBS,IO_L33N_1,UNUSED,,1,,,,,,,,,
D1,X<29>,IOB,IO_L54N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
D2,,,VCCO_3,,,3,,,,,any******,,,,
D3,X<28>,IOB,IO_L54P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
D4,X<26>,IOB,IO_L53P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
D5,Y<3>,IOB,IO_L3P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
D6,,,NC,,,,,,,,,,,,
D7,,,NC,,,,,,,,,,,,
D8,Y<12>,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
D9,,,VCCO_0,,,0,,,,,2.50,,,,
D10,Y<19>,IOB,IO_L39P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
D11,Y<27>,IOB,IO_L64P_SCP5_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
D12,,,TDO,,,,,,,,,,,,
D13,,IOBM,IO_L35P_1,UNUSED,,1,,,,,,,,,
D14,,,VCCO_1,,,1,,,,,any******,,,,
D15,,IOBS,IO_L35N_1,UNUSED,,1,,,,,,,,,
E1,X<25>,IOB,IO_L52N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
E2,X<24>,IOB,IO_L52P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
E3,X<27>,IOB,IO_L53N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
E4,,,NC,,,,,,,,,,,,
E5,,,NC,,,,,,,,,,,,
E6,,,NC,,,,,,,,,,,,
E7,Y<11>,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
E8,,,NC,,,,,,,,,,,,
E9,Y<22>,IOB,IO_L40N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
E10,,,TDI,,,,,,,,,,,,
E11,,,GND,,,,,,,,,,,,
E12,,,VCCAUX,,,,,,,,2.5,,,,
E13,,,TMS,,,,,,,,,,,,
E14,,IOBM,IO_L37P_1,UNUSED,,1,,,,,,,,,
E15,,IOBS,IO_L37N_1,UNUSED,,1,,,,,,,,,
F1,X<23>,IOB,IO_L46N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
F2,,,GND,,,,,,,,,,,,
F3,X<22>,IOB,IO_L46P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
F4,,,NC,,,,,,,,,,,,
F5,,,NC,,,,,,,,,,,,
F6,,,GND,,,,,,,,,,,,
F7,,,VCCAUX,,,,,,,,2.5,,,,
F8,,,NC,,,,,,,,,,,,
F9,,,VCCINT,,,,,,,,1.2,,,,
F10,Y<21>,IOB,IO_L40P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
F11,,,NC,,,,,,,,,,,,
F12,,,NC,,,,,,,,,,,,
F13,,IOBM,IO_L39P_1,UNUSED,,1,,,,,,,,,
F14,,,GND,,,,,,,,,,,,
F15,,IOBS,IO_L39N_1,UNUSED,,1,,,,,,,,,
G1,X<12>,IOB,IO_L44N_GCLK20_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
G2,X<15>,IOB,IO_L44P_GCLK21_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
G3,,,NC,,,,,,,,,,,,
G4,,,VCCO_3,,,3,,,,,any******,,,,
G5,,,NC,,,,,,,,,,,,
G6,,,VCCINT,,,,,,,,1.2,,,,
G7,,,GND,,,,,,,,,,,,
G8,,,VCCINT,,,,,,,,1.2,,,,
G9,,,GND,,,,,,,,,,,,
G10,,,VCCAUX,,,,,,,,2.5,,,,
G11,,,NC,,,,,,,,,,,,
G12,,,NC,,,,,,,,,,,,
G13,,,NC,,,,,,,,,,,,
G14,,IOBM,IO_L41P_GCLK9_IRDY1_1,UNUSED,,1,,,,,,,,,
G15,,IOBS,IO_L41N_GCLK8_1,UNUSED,,1,,,,,,,,,
H1,X<18>,IOB,IO_L42N_GCLK24_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
H2,,,VCCO_3,,,3,,,,,any******,,,,
H3,X<14>,IOB,IO_L42P_GCLK25_TRDY2_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
H4,,,NC,,,,,,,,,,,,
H5,,,NC,,,,,,,,,,,,
H6,,,NC,,,,,,,,,,,,
H7,,,VCCINT,,,,,,,,1.2,,,,
H8,,,GND,,,,,,,,,,,,
H9,,,VCCINT,,,,,,,,1.2,,,,
H10,,,NC,,,,,,,,,,,,
H11,,,NC,,,,,,,,,,,,
H12,,,NC,,,,,,,,,,,,
H13,,IOBM,IO_L42P_GCLK7_1,UNUSED,,1,,,,,,,,,
H14,,,VCCO_1,,,1,,,,,any******,,,,
H15,,IOBS,IO_L42N_GCLK6_TRDY1_1,UNUSED,,1,,,,,,,,,
J1,X<16>,IOB,IO_L41N_GCLK26_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
J2,X<19>,IOB,IO_L41P_GCLK27_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
J3,X<17>,IOB,IO_L43N_GCLK22_IRDY2_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
J4,X<21>,IOB,IO_L45N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
J5,,,NC,,,,,,,,,,,,
J6,,,VCCAUX,,,,,,,,2.5,,,,
J7,,,GND,,,,,,,,,,,,
J8,,,VCCINT,,,,,,,,1.2,,,,
J9,,,GND,,,,,,,,,,,,
J10,,,VCCINT,,,,,,,,1.2,,,,
J11,,IOBM,IO_L36P_1,UNUSED,,1,,,,,,,,,
J12,,,VCCO_1,,,1,,,,,any******,,,,
J13,,IOBS,IO_L36N_1,UNUSED,,1,,,,,,,,,
J14,,IOBM,IO_L43P_GCLK5_1,UNUSED,,1,,,,,,,,,
J15,,IOBS,IO_L43N_GCLK4_1,UNUSED,,1,,,,,,,,,
K1,X<11>,IOB,IO_L40N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
K2,,,GND,,,,,,,,,,,,
K3,X<10>,IOB,IO_L40P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
K4,X<20>,IOB,IO_L43P_GCLK23_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
K5,X<13>,IOB,IO_L45P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
K6,,,GND,,,,,,,,,,,,
K7,,,VCCINT,,,,,,,,1.2,,,,
K8,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
K9,,,VCCAUX,,,,,,,,2.5,,,,
K10,,IOBM,IO_L38P_1,UNUSED,,1,,,,,,,,,
K11,,IOBS,IO_L38N_1,UNUSED,,1,,,,,,,,,
K12,,IOBM,IO_L40P_GCLK11_1,UNUSED,,1,,,,,,,,,
K13,,IOBM,IO_L44P_1,UNUSED,,1,,,,,,,,,
K14,,,GND,,,,,,,,,,,,
K15,,IOBS,IO_L44N_1,UNUSED,,1,,,,,,,,,
L1,X<9>,IOB,IO_L39N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
L2,X<8>,IOB,IO_L39P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
L3,X<5>,IOB,IO_L1N_VREF_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
L4,,,VCCAUX,,,,,,,,2.5,,,,
L5,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
L6,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
L7,,,NC,,,,,,,,,,,,
L8,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
L9,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
L10,,,CMPCS_B_2,,,,,,,,,,,,
L11,,,GND,,,,,,,,,,,,
L12,,IOBS,IO_L40N_GCLK10_1,UNUSED,,1,,,,,,,,,
L13,,,SUSPEND,,,,,,,,,,,,
L14,,IOBM,IO_L45P_1,UNUSED,,1,,,,,,,,,
L15,,IOBS,IO_L45N_1,UNUSED,,1,,,,,,,,,
M1,X<1>,IOB,IO_L38N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
M2,,,VCCO_3,,,3,,,,,any******,,,,
M3,X<0>,IOB,IO_L38P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
M4,X<4>,IOB,IO_L1P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
M5,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
M6,,,NC,,,,,,,,,,,,
M7,,,VCCO_2,,,2,,,,,any******,,,,
M8,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
M9,,,NC,,,,,,,,,,,,
M10,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,,
M11,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
M12,,,VCCAUX,,,,,,,,2.5,,,,
M13,,IOBM,IO_L46P_1,UNUSED,,1,,,,,,,,,
M14,,,VCCO_1,,,1,,,,,any******,,,,
M15,,IOBS,IO_L46N_1,UNUSED,,1,,,,,,,,,
N1,X<7>,IOB,IO_L37N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
N2,X<6>,IOB,IO_L37P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
N3,,,GND,,,,,,,,,,,,
N4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
N5,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
N6,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
N7,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,,
N8,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
N9,,,NC,,,,,,,,,,,,
N10,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
N11,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
N12,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
N13,,,GND,,,,,,,,,,,,
N14,,IOBM,IO_L47P_1,UNUSED,,1,,,,,,,,,
N15,,IOBS,IO_L47N_1,UNUSED,,1,,,,,,,,,
P1,X<3>,IOB,IO_L2N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
P2,X<2>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
P3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
P4,,,VCCO_2,,,2,,,,,any******,,,,
P5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
P6,,,GND,,,,,,,,,,,,
P7,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,
P8,,,VCCO_2,,,2,,,,,any******,,,,
P9,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
P10,,,GND,,,,,,,,,,,,
P11,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
P12,,,VCCO_2,,,2,,,,,any******,,,,
P13,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
P14,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
P15,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
R1,,,GND,,,,,,,,,,,,
R2,,,PROGRAM_B_2,,,,,,,,,,,,
R3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
R4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,,
R5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
R6,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
R7,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,,
R8,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
R9,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
R10,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,,
R11,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
R12,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
R13,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
R14,,,DONE_2,,,,,,,,,,,,
R15,,,GND,,,,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
1 #Release 14.7 - par P.20131013 (lin64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Sat Aug 24 12:14:30 2019
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
8 # to support parsing.
9 #
10 #INPUT FILE: SpecialCasesCheck_map.ncd
11 #OUTPUT FILE: SpecialCasesCheck_pad.csv
12 #PART TYPE: xa6slx4
13 #SPEED GRADE: -3
14 #PACKAGE: csg225
15 #
16 # Pinout by Pin Number:
17 #
18 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
19 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
20 A1,,,GND,,,,,,,,,,,,
21 A2,Y<0>,IOB,IO_L1N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
22 A3,Y<2>,IOB,IO_L2N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
23 A4,Y<6>,IOB,IO_L4N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
24 A5,Y<8>,IOB,IO_L6N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
25 A6,Y<10>,IOB,IO_L33N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
26 A7,Y<14>,IOB,IO_L35N_GCLK16_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
27 A8,Y<16>,IOB,IO_L36N_GCLK14_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
28 A9,Y<18>,IOB,IO_L37N_GCLK12_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
29 A10,Y<24>,IOB,IO_L62N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
30 A11,Y<26>,IOB,IO_L63N_SCP6_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
31 A12,isZero,IOB,IO_L66N_SCP0_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,UNLOCATED,NO,NONE,
32 A13,Y<30>,IOB,IO_L65N_SCP2_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
33 A14,,,TCK,,,,,,,,,,,,
34 A15,,,GND,,,,,,,,,,,,
35 B1,,,VCCAUX,,,,,,,,2.5,,,,
36 B2,isNaN,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS25*,0,12,SLOW,,,,UNLOCATED,NO,NONE,
37 B3,Y<1>,IOB,IO_L2P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
38 B4,,,VCCO_0,,,0,,,,,2.50,,,,
39 B5,Y<9>,IOB,IO_L6P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
40 B6,,,GND,,,,,,,,,,,,
41 B7,Y<13>,IOB,IO_L35P_GCLK17_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
42 B8,,,VCCO_0,,,0,,,,,2.50,,,,
43 B9,Y<17>,IOB,IO_L37P_GCLK13_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
44 B10,,,GND,,,,,,,,,,,,
45 B11,Y<25>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
46 B12,,,VCCO_0,,,0,,,,,2.50,,,,
47 B13,Y<29>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
48 B14,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,,
49 B15,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,,
50 C1,X<31>,IOB,IO_L83N_VREF_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
51 C2,X<30>,IOB,IO_L83P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
52 C3,,,GND,,,,,,,,,,,,
53 C4,Y<5>,IOB,IO_L4P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
54 C5,Y<4>,IOB,IO_L3N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
55 C6,Y<7>,IOB,IO_L33P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
56 C7,,,NC,,,,,,,,,,,,
57 C8,Y<15>,IOB,IO_L36P_GCLK15_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
58 C9,Y<20>,IOB,IO_L39N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
59 C10,Y<23>,IOB,IO_L62P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
60 C11,Y<28>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
61 C12,Y<31>,IOB,IO_L66P_SCP1_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
62 C13,,,GND,,,,,,,,,,,,
63 C14,,IOBM,IO_L33P_1,UNUSED,,1,,,,,,,,,
64 C15,,IOBS,IO_L33N_1,UNUSED,,1,,,,,,,,,
65 D1,X<29>,IOB,IO_L54N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
66 D2,,,VCCO_3,,,3,,,,,any******,,,,
67 D3,X<28>,IOB,IO_L54P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
68 D4,X<26>,IOB,IO_L53P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
69 D5,Y<3>,IOB,IO_L3P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
70 D6,,,NC,,,,,,,,,,,,
71 D7,,,NC,,,,,,,,,,,,
72 D8,Y<12>,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
73 D9,,,VCCO_0,,,0,,,,,2.50,,,,
74 D10,Y<19>,IOB,IO_L39P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
75 D11,Y<27>,IOB,IO_L64P_SCP5_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
76 D12,,,TDO,,,,,,,,,,,,
77 D13,,IOBM,IO_L35P_1,UNUSED,,1,,,,,,,,,
78 D14,,,VCCO_1,,,1,,,,,any******,,,,
79 D15,,IOBS,IO_L35N_1,UNUSED,,1,,,,,,,,,
80 E1,X<25>,IOB,IO_L52N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
81 E2,X<24>,IOB,IO_L52P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
82 E3,X<27>,IOB,IO_L53N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
83 E4,,,NC,,,,,,,,,,,,
84 E5,,,NC,,,,,,,,,,,,
85 E6,,,NC,,,,,,,,,,,,
86 E7,Y<11>,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
87 E8,,,NC,,,,,,,,,,,,
88 E9,Y<22>,IOB,IO_L40N_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
89 E10,,,TDI,,,,,,,,,,,,
90 E11,,,GND,,,,,,,,,,,,
91 E12,,,VCCAUX,,,,,,,,2.5,,,,
92 E13,,,TMS,,,,,,,,,,,,
93 E14,,IOBM,IO_L37P_1,UNUSED,,1,,,,,,,,,
94 E15,,IOBS,IO_L37N_1,UNUSED,,1,,,,,,,,,
95 F1,X<23>,IOB,IO_L46N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
96 F2,,,GND,,,,,,,,,,,,
97 F3,X<22>,IOB,IO_L46P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
98 F4,,,NC,,,,,,,,,,,,
99 F5,,,NC,,,,,,,,,,,,
100 F6,,,GND,,,,,,,,,,,,
101 F7,,,VCCAUX,,,,,,,,2.5,,,,
102 F8,,,NC,,,,,,,,,,,,
103 F9,,,VCCINT,,,,,,,,1.2,,,,
104 F10,Y<21>,IOB,IO_L40P_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
105 F11,,,NC,,,,,,,,,,,,
106 F12,,,NC,,,,,,,,,,,,
107 F13,,IOBM,IO_L39P_1,UNUSED,,1,,,,,,,,,
108 F14,,,GND,,,,,,,,,,,,
109 F15,,IOBS,IO_L39N_1,UNUSED,,1,,,,,,,,,
110 G1,X<12>,IOB,IO_L44N_GCLK20_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
111 G2,X<15>,IOB,IO_L44P_GCLK21_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
112 G3,,,NC,,,,,,,,,,,,
113 G4,,,VCCO_3,,,3,,,,,any******,,,,
114 G5,,,NC,,,,,,,,,,,,
115 G6,,,VCCINT,,,,,,,,1.2,,,,
116 G7,,,GND,,,,,,,,,,,,
117 G8,,,VCCINT,,,,,,,,1.2,,,,
118 G9,,,GND,,,,,,,,,,,,
119 G10,,,VCCAUX,,,,,,,,2.5,,,,
120 G11,,,NC,,,,,,,,,,,,
121 G12,,,NC,,,,,,,,,,,,
122 G13,,,NC,,,,,,,,,,,,
123 G14,,IOBM,IO_L41P_GCLK9_IRDY1_1,UNUSED,,1,,,,,,,,,
124 G15,,IOBS,IO_L41N_GCLK8_1,UNUSED,,1,,,,,,,,,
125 H1,X<18>,IOB,IO_L42N_GCLK24_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
126 H2,,,VCCO_3,,,3,,,,,any******,,,,
127 H3,X<14>,IOB,IO_L42P_GCLK25_TRDY2_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
128 H4,,,NC,,,,,,,,,,,,
129 H5,,,NC,,,,,,,,,,,,
130 H6,,,NC,,,,,,,,,,,,
131 H7,,,VCCINT,,,,,,,,1.2,,,,
132 H8,,,GND,,,,,,,,,,,,
133 H9,,,VCCINT,,,,,,,,1.2,,,,
134 H10,,,NC,,,,,,,,,,,,
135 H11,,,NC,,,,,,,,,,,,
136 H12,,,NC,,,,,,,,,,,,
137 H13,,IOBM,IO_L42P_GCLK7_1,UNUSED,,1,,,,,,,,,
138 H14,,,VCCO_1,,,1,,,,,any******,,,,
139 H15,,IOBS,IO_L42N_GCLK6_TRDY1_1,UNUSED,,1,,,,,,,,,
140 J1,X<16>,IOB,IO_L41N_GCLK26_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
141 J2,X<19>,IOB,IO_L41P_GCLK27_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
142 J3,X<17>,IOB,IO_L43N_GCLK22_IRDY2_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
143 J4,X<21>,IOB,IO_L45N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
144 J5,,,NC,,,,,,,,,,,,
145 J6,,,VCCAUX,,,,,,,,2.5,,,,
146 J7,,,GND,,,,,,,,,,,,
147 J8,,,VCCINT,,,,,,,,1.2,,,,
148 J9,,,GND,,,,,,,,,,,,
149 J10,,,VCCINT,,,,,,,,1.2,,,,
150 J11,,IOBM,IO_L36P_1,UNUSED,,1,,,,,,,,,
151 J12,,,VCCO_1,,,1,,,,,any******,,,,
152 J13,,IOBS,IO_L36N_1,UNUSED,,1,,,,,,,,,
153 J14,,IOBM,IO_L43P_GCLK5_1,UNUSED,,1,,,,,,,,,
154 J15,,IOBS,IO_L43N_GCLK4_1,UNUSED,,1,,,,,,,,,
155 K1,X<11>,IOB,IO_L40N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
156 K2,,,GND,,,,,,,,,,,,
157 K3,X<10>,IOB,IO_L40P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
158 K4,X<20>,IOB,IO_L43P_GCLK23_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
159 K5,X<13>,IOB,IO_L45P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
160 K6,,,GND,,,,,,,,,,,,
161 K7,,,VCCINT,,,,,,,,1.2,,,,
162 K8,,IOBM,IO_L31P_GCLK31_D14_2,UNUSED,,2,,,,,,,,,
163 K9,,,VCCAUX,,,,,,,,2.5,,,,
164 K10,,IOBM,IO_L38P_1,UNUSED,,1,,,,,,,,,
165 K11,,IOBS,IO_L38N_1,UNUSED,,1,,,,,,,,,
166 K12,,IOBM,IO_L40P_GCLK11_1,UNUSED,,1,,,,,,,,,
167 K13,,IOBM,IO_L44P_1,UNUSED,,1,,,,,,,,,
168 K14,,,GND,,,,,,,,,,,,
169 K15,,IOBS,IO_L44N_1,UNUSED,,1,,,,,,,,,
170 L1,X<9>,IOB,IO_L39N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
171 L2,X<8>,IOB,IO_L39P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
172 L3,X<5>,IOB,IO_L1N_VREF_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
173 L4,,,VCCAUX,,,,,,,,2.5,,,,
174 L5,,IOBS,IO_L62N_D6_2,UNUSED,,2,,,,,,,,,
175 L6,,IOBM,IO_L62P_D5_2,UNUSED,,2,,,,,,,,,
176 L7,,,NC,,,,,,,,,,,,
177 L8,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,,
178 L9,,IOBM,IO_L14P_D11_2,UNUSED,,2,,,,,,,,,
179 L10,,,CMPCS_B_2,,,,,,,,,,,,
180 L11,,,GND,,,,,,,,,,,,
181 L12,,IOBS,IO_L40N_GCLK10_1,UNUSED,,1,,,,,,,,,
182 L13,,,SUSPEND,,,,,,,,,,,,
183 L14,,IOBM,IO_L45P_1,UNUSED,,1,,,,,,,,,
184 L15,,IOBS,IO_L45N_1,UNUSED,,1,,,,,,,,,
185 M1,X<1>,IOB,IO_L38N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
186 M2,,,VCCO_3,,,3,,,,,any******,,,,
187 M3,X<0>,IOB,IO_L38P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
188 M4,X<4>,IOB,IO_L1P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
189 M5,,IOBM,IO_L64P_D8_2,UNUSED,,2,,,,,,,,,
190 M6,,,NC,,,,,,,,,,,,
191 M7,,,VCCO_2,,,2,,,,,any******,,,,
192 M8,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,,
193 M9,,,NC,,,,,,,,,,,,
194 M10,,IOBS,IO_L14N_D12_2,UNUSED,,2,,,,,,,,,
195 M11,,IOBM,IO_L12P_D1_MISO2_2,UNUSED,,2,,,,,,,,,
196 M12,,,VCCAUX,,,,,,,,2.5,,,,
197 M13,,IOBM,IO_L46P_1,UNUSED,,1,,,,,,,,,
198 M14,,,VCCO_1,,,1,,,,,any******,,,,
199 M15,,IOBS,IO_L46N_1,UNUSED,,1,,,,,,,,,
200 N1,X<7>,IOB,IO_L37N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
201 N2,X<6>,IOB,IO_L37P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
202 N3,,,GND,,,,,,,,,,,,
203 N4,,IOBM,IO_L63P_2,UNUSED,,2,,,,,,,,,
204 N5,,IOBS,IO_L64N_D9_2,UNUSED,,2,,,,,,,,,
205 N6,,IOBM,IO_L48P_D7_2,UNUSED,,2,,,,,,,,,
206 N7,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,,
207 N8,,IOBM,IO_L29P_GCLK3_2,UNUSED,,2,,,,,,,,,
208 N9,,,NC,,,,,,,,,,,,
209 N10,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,,
210 N11,,IOBS,IO_L12N_D2_MISO3_2,UNUSED,,2,,,,,,,,,
211 N12,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,,
212 N13,,,GND,,,,,,,,,,,,
213 N14,,IOBM,IO_L47P_1,UNUSED,,1,,,,,,,,,
214 N15,,IOBS,IO_L47N_1,UNUSED,,1,,,,,,,,,
215 P1,X<3>,IOB,IO_L2N_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
216 P2,X<2>,IOB,IO_L2P_3,INPUT,LVCMOS25*,3,,,,NONE,,UNLOCATED,NO,NONE,
217 P3,,IOBM,IO_L65P_INIT_B_2,UNUSED,,2,,,,,,,,,
218 P4,,,VCCO_2,,,2,,,,,any******,,,,
219 P5,,IOBM,IO_L49P_D3_2,UNUSED,,2,,,,,,,,,
220 P6,,,GND,,,,,,,,,,,,
221 P7,,IOBM,IO_L32P_GCLK29_2,UNUSED,,2,,,,,,,,,
222 P8,,,VCCO_2,,,2,,,,,any******,,,,
223 P9,,IOBM,IO_L16P_2,UNUSED,,2,,,,,,,,,
224 P10,,,GND,,,,,,,,,,,,
225 P11,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,,
226 P12,,,VCCO_2,,,2,,,,,any******,,,,
227 P13,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,,
228 P14,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,,
229 P15,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,,
230 R1,,,GND,,,,,,,,,,,,
231 R2,,,PROGRAM_B_2,,,,,,,,,,,,
232 R3,,IOBS,IO_L65N_CSO_B_2,UNUSED,,2,,,,,,,,,
233 R4,,IOBS,IO_L63N_2,UNUSED,,2,,,,,,,,,
234 R5,,IOBS,IO_L49N_D4_2,UNUSED,,2,,,,,,,,,
235 R6,,IOBS,IO_L48N_RDWR_B_VREF_2,UNUSED,,2,,,,,,,,,
236 R7,,IOBS,IO_L32N_GCLK28_2,UNUSED,,2,,,,,,,,,
237 R8,,IOBS,IO_L29N_GCLK2_2,UNUSED,,2,,,,,,,,,
238 R9,,IOBS,IO_L16N_VREF_2,UNUSED,,2,,,,,,,,,
239 R10,,IOBS,IO_L13N_D10_2,UNUSED,,2,,,,,,,,,
240 R11,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,,
241 R12,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,,
242 R13,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,,
243 R14,,,DONE_2,,,,,,,,,,,,
244 R15,,,GND,,,,,,,,,,,,
245 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
246 #
247 #* Default value.
248 #** This default Pullup/Pulldown value can be overridden in Bitgen.
249 #****** Special VCCO requirements may apply. Please consult the device
250 # family datasheet for specific guideline on VCCO requirements.
251 #
252 #
253 #

255
SpecialCasesCheck_pad.txt Normal file
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@@ -0,0 +1,255 @@
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 24 12:14:30 2019
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: SpecialCasesCheck_map.ncd
OUTPUT FILE: SpecialCasesCheck_pad.txt
PART TYPE: xa6slx4
SPEED GRADE: -3
PACKAGE: csg225
Pinout by Pin Number:
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A1 | | |GND | | | | | | | | | | | |
|A2 |Y<0> |IOB |IO_L1N_VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A3 |Y<2> |IOB |IO_L2N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A4 |Y<6> |IOB |IO_L4N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A5 |Y<8> |IOB |IO_L6N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A6 |Y<10> |IOB |IO_L33N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A7 |Y<14> |IOB |IO_L35N_GCLK16_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A8 |Y<16> |IOB |IO_L36N_GCLK14_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A9 |Y<18> |IOB |IO_L37N_GCLK12_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A10 |Y<24> |IOB |IO_L62N_VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A11 |Y<26> |IOB |IO_L63N_SCP6_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A12 |isZero |IOB |IO_L66N_SCP0_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |UNLOCATED |NO |NONE |
|A13 |Y<30> |IOB |IO_L65N_SCP2_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|A14 | | |TCK | | | | | | | | | | | |
|A15 | | |GND | | | | | | | | | | | |
|B1 | | |VCCAUX | | | | | | | |2.5 | | | |
|B2 |isNaN |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW | | | |UNLOCATED |NO |NONE |
|B3 |Y<1> |IOB |IO_L2P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B4 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B5 |Y<9> |IOB |IO_L6P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B6 | | |GND | | | | | | | | | | | |
|B7 |Y<13> |IOB |IO_L35P_GCLK17_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B8 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B9 |Y<17> |IOB |IO_L37P_GCLK13_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B10 | | |GND | | | | | | | | | | | |
|B11 |Y<25> |IOB |IO_L63P_SCP7_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B12 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|B13 |Y<29> |IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|B14 | |IOBM |IO_L1P_1 |UNUSED | |1 | | | | | | | | |
|B15 | |IOBS |IO_L1N_VREF_1 |UNUSED | |1 | | | | | | | | |
|C1 |X<31> |IOB |IO_L83N_VREF_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|C2 |X<30> |IOB |IO_L83P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|C3 | | |GND | | | | | | | | | | | |
|C4 |Y<5> |IOB |IO_L4P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C5 |Y<4> |IOB |IO_L3N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C6 |Y<7> |IOB |IO_L33P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C7 | | |NC | | | | | | | | | | | |
|C8 |Y<15> |IOB |IO_L36P_GCLK15_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C9 |Y<20> |IOB |IO_L39N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C10 |Y<23> |IOB |IO_L62P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C11 |Y<28> |IOB |IO_L64N_SCP4_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C12 |Y<31> |IOB |IO_L66P_SCP1_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|C13 | | |GND | | | | | | | | | | | |
|C14 | |IOBM |IO_L33P_1 |UNUSED | |1 | | | | | | | | |
|C15 | |IOBS |IO_L33N_1 |UNUSED | |1 | | | | | | | | |
|D1 |X<29> |IOB |IO_L54N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|D2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|D3 |X<28> |IOB |IO_L54P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|D4 |X<26> |IOB |IO_L53P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|D5 |Y<3> |IOB |IO_L3P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|D6 | | |NC | | | | | | | | | | | |
|D7 | | |NC | | | | | | | | | | | |
|D8 |Y<12> |IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|D9 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|D10 |Y<19> |IOB |IO_L39P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|D11 |Y<27> |IOB |IO_L64P_SCP5_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|D12 | | |TDO | | | | | | | | | | | |
|D13 | |IOBM |IO_L35P_1 |UNUSED | |1 | | | | | | | | |
|D14 | | |VCCO_1 | | |1 | | | | |any******| | | |
|D15 | |IOBS |IO_L35N_1 |UNUSED | |1 | | | | | | | | |
|E1 |X<25> |IOB |IO_L52N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|E2 |X<24> |IOB |IO_L52P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|E3 |X<27> |IOB |IO_L53N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|E4 | | |NC | | | | | | | | | | | |
|E5 | | |NC | | | | | | | | | | | |
|E6 | | |NC | | | | | | | | | | | |
|E7 |Y<11> |IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|E8 | | |NC | | | | | | | | | | | |
|E9 |Y<22> |IOB |IO_L40N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|E10 | | |TDI | | | | | | | | | | | |
|E11 | | |GND | | | | | | | | | | | |
|E12 | | |VCCAUX | | | | | | | |2.5 | | | |
|E13 | | |TMS | | | | | | | | | | | |
|E14 | |IOBM |IO_L37P_1 |UNUSED | |1 | | | | | | | | |
|E15 | |IOBS |IO_L37N_1 |UNUSED | |1 | | | | | | | | |
|F1 |X<23> |IOB |IO_L46N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|F2 | | |GND | | | | | | | | | | | |
|F3 |X<22> |IOB |IO_L46P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|F4 | | |NC | | | | | | | | | | | |
|F5 | | |NC | | | | | | | | | | | |
|F6 | | |GND | | | | | | | | | | | |
|F7 | | |VCCAUX | | | | | | | |2.5 | | | |
|F8 | | |NC | | | | | | | | | | | |
|F9 | | |VCCINT | | | | | | | |1.2 | | | |
|F10 |Y<21> |IOB |IO_L40P_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|F11 | | |NC | | | | | | | | | | | |
|F12 | | |NC | | | | | | | | | | | |
|F13 | |IOBM |IO_L39P_1 |UNUSED | |1 | | | | | | | | |
|F14 | | |GND | | | | | | | | | | | |
|F15 | |IOBS |IO_L39N_1 |UNUSED | |1 | | | | | | | | |
|G1 |X<12> |IOB |IO_L44N_GCLK20_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|G2 |X<15> |IOB |IO_L44P_GCLK21_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|G3 | | |NC | | | | | | | | | | | |
|G4 | | |VCCO_3 | | |3 | | | | |any******| | | |
|G5 | | |NC | | | | | | | | | | | |
|G6 | | |VCCINT | | | | | | | |1.2 | | | |
|G7 | | |GND | | | | | | | | | | | |
|G8 | | |VCCINT | | | | | | | |1.2 | | | |
|G9 | | |GND | | | | | | | | | | | |
|G10 | | |VCCAUX | | | | | | | |2.5 | | | |
|G11 | | |NC | | | | | | | | | | | |
|G12 | | |NC | | | | | | | | | | | |
|G13 | | |NC | | | | | | | | | | | |
|G14 | |IOBM |IO_L41P_GCLK9_IRDY1_1 |UNUSED | |1 | | | | | | | | |
|G15 | |IOBS |IO_L41N_GCLK8_1 |UNUSED | |1 | | | | | | | | |
|H1 |X<18> |IOB |IO_L42N_GCLK24_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|H2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|H3 |X<14> |IOB |IO_L42P_GCLK25_TRDY2_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|H4 | | |NC | | | | | | | | | | | |
|H5 | | |NC | | | | | | | | | | | |
|H6 | | |NC | | | | | | | | | | | |
|H7 | | |VCCINT | | | | | | | |1.2 | | | |
|H8 | | |GND | | | | | | | | | | | |
|H9 | | |VCCINT | | | | | | | |1.2 | | | |
|H10 | | |NC | | | | | | | | | | | |
|H11 | | |NC | | | | | | | | | | | |
|H12 | | |NC | | | | | | | | | | | |
|H13 | |IOBM |IO_L42P_GCLK7_1 |UNUSED | |1 | | | | | | | | |
|H14 | | |VCCO_1 | | |1 | | | | |any******| | | |
|H15 | |IOBS |IO_L42N_GCLK6_TRDY1_1 |UNUSED | |1 | | | | | | | | |
|J1 |X<16> |IOB |IO_L41N_GCLK26_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J2 |X<19> |IOB |IO_L41P_GCLK27_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J3 |X<17> |IOB |IO_L43N_GCLK22_IRDY2_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J4 |X<21> |IOB |IO_L45N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|J5 | | |NC | | | | | | | | | | | |
|J6 | | |VCCAUX | | | | | | | |2.5 | | | |
|J7 | | |GND | | | | | | | | | | | |
|J8 | | |VCCINT | | | | | | | |1.2 | | | |
|J9 | | |GND | | | | | | | | | | | |
|J10 | | |VCCINT | | | | | | | |1.2 | | | |
|J11 | |IOBM |IO_L36P_1 |UNUSED | |1 | | | | | | | | |
|J12 | | |VCCO_1 | | |1 | | | | |any******| | | |
|J13 | |IOBS |IO_L36N_1 |UNUSED | |1 | | | | | | | | |
|J14 | |IOBM |IO_L43P_GCLK5_1 |UNUSED | |1 | | | | | | | | |
|J15 | |IOBS |IO_L43N_GCLK4_1 |UNUSED | |1 | | | | | | | | |
|K1 |X<11> |IOB |IO_L40N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K2 | | |GND | | | | | | | | | | | |
|K3 |X<10> |IOB |IO_L40P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K4 |X<20> |IOB |IO_L43P_GCLK23_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K5 |X<13> |IOB |IO_L45P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|K6 | | |GND | | | | | | | | | | | |
|K7 | | |VCCINT | | | | | | | |1.2 | | | |
|K8 | |IOBM |IO_L31P_GCLK31_D14_2 |UNUSED | |2 | | | | | | | | |
|K9 | | |VCCAUX | | | | | | | |2.5 | | | |
|K10 | |IOBM |IO_L38P_1 |UNUSED | |1 | | | | | | | | |
|K11 | |IOBS |IO_L38N_1 |UNUSED | |1 | | | | | | | | |
|K12 | |IOBM |IO_L40P_GCLK11_1 |UNUSED | |1 | | | | | | | | |
|K13 | |IOBM |IO_L44P_1 |UNUSED | |1 | | | | | | | | |
|K14 | | |GND | | | | | | | | | | | |
|K15 | |IOBS |IO_L44N_1 |UNUSED | |1 | | | | | | | | |
|L1 |X<9> |IOB |IO_L39N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|L2 |X<8> |IOB |IO_L39P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|L3 |X<5> |IOB |IO_L1N_VREF_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|L4 | | |VCCAUX | | | | | | | |2.5 | | | |
|L5 | |IOBS |IO_L62N_D6_2 |UNUSED | |2 | | | | | | | | |
|L6 | |IOBM |IO_L62P_D5_2 |UNUSED | |2 | | | | | | | | |
|L7 | | |NC | | | | | | | | | | | |
|L8 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | |
|L9 | |IOBM |IO_L14P_D11_2 |UNUSED | |2 | | | | | | | | |
|L10 | | |CMPCS_B_2 | | | | | | | | | | | |
|L11 | | |GND | | | | | | | | | | | |
|L12 | |IOBS |IO_L40N_GCLK10_1 |UNUSED | |1 | | | | | | | | |
|L13 | | |SUSPEND | | | | | | | | | | | |
|L14 | |IOBM |IO_L45P_1 |UNUSED | |1 | | | | | | | | |
|L15 | |IOBS |IO_L45N_1 |UNUSED | |1 | | | | | | | | |
|M1 |X<1> |IOB |IO_L38N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M2 | | |VCCO_3 | | |3 | | | | |any******| | | |
|M3 |X<0> |IOB |IO_L38P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M4 |X<4> |IOB |IO_L1P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|M5 | |IOBM |IO_L64P_D8_2 |UNUSED | |2 | | | | | | | | |
|M6 | | |NC | | | | | | | | | | | |
|M7 | | |VCCO_2 | | |2 | | | | |any******| | | |
|M8 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | |
|M9 | | |NC | | | | | | | | | | | |
|M10 | |IOBS |IO_L14N_D12_2 |UNUSED | |2 | | | | | | | | |
|M11 | |IOBM |IO_L12P_D1_MISO2_2 |UNUSED | |2 | | | | | | | | |
|M12 | | |VCCAUX | | | | | | | |2.5 | | | |
|M13 | |IOBM |IO_L46P_1 |UNUSED | |1 | | | | | | | | |
|M14 | | |VCCO_1 | | |1 | | | | |any******| | | |
|M15 | |IOBS |IO_L46N_1 |UNUSED | |1 | | | | | | | | |
|N1 |X<7> |IOB |IO_L37N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|N2 |X<6> |IOB |IO_L37P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|N3 | | |GND | | | | | | | | | | | |
|N4 | |IOBM |IO_L63P_2 |UNUSED | |2 | | | | | | | | |
|N5 | |IOBS |IO_L64N_D9_2 |UNUSED | |2 | | | | | | | | |
|N6 | |IOBM |IO_L48P_D7_2 |UNUSED | |2 | | | | | | | | |
|N7 | |IOBS |IO_L30N_GCLK0_USERCCLK_2 |UNUSED | |2 | | | | | | | | |
|N8 | |IOBM |IO_L29P_GCLK3_2 |UNUSED | |2 | | | | | | | | |
|N9 | | |NC | | | | | | | | | | | |
|N10 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | |
|N11 | |IOBS |IO_L12N_D2_MISO3_2 |UNUSED | |2 | | | | | | | | |
|N12 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | |
|N13 | | |GND | | | | | | | | | | | |
|N14 | |IOBM |IO_L47P_1 |UNUSED | |1 | | | | | | | | |
|N15 | |IOBS |IO_L47N_1 |UNUSED | |1 | | | | | | | | |
|P1 |X<3> |IOB |IO_L2N_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|P2 |X<2> |IOB |IO_L2P_3 |INPUT |LVCMOS25* |3 | | | |NONE | |UNLOCATED |NO |NONE |
|P3 | |IOBM |IO_L65P_INIT_B_2 |UNUSED | |2 | | | | | | | | |
|P4 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P5 | |IOBM |IO_L49P_D3_2 |UNUSED | |2 | | | | | | | | |
|P6 | | |GND | | | | | | | | | | | |
|P7 | |IOBM |IO_L32P_GCLK29_2 |UNUSED | |2 | | | | | | | | |
|P8 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P9 | |IOBM |IO_L16P_2 |UNUSED | |2 | | | | | | | | |
|P10 | | |GND | | | | | | | | | | | |
|P11 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED | |2 | | | | | | | | |
|P12 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P13 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | |
|P14 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | |
|P15 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | |
|R1 | | |GND | | | | | | | | | | | |
|R2 | | |PROGRAM_B_2 | | | | | | | | | | | |
|R3 | |IOBS |IO_L65N_CSO_B_2 |UNUSED | |2 | | | | | | | | |
|R4 | |IOBS |IO_L63N_2 |UNUSED | |2 | | | | | | | | |
|R5 | |IOBS |IO_L49N_D4_2 |UNUSED | |2 | | | | | | | | |
|R6 | |IOBS |IO_L48N_RDWR_B_VREF_2 |UNUSED | |2 | | | | | | | | |
|R7 | |IOBS |IO_L32N_GCLK28_2 |UNUSED | |2 | | | | | | | | |
|R8 | |IOBS |IO_L29N_GCLK2_2 |UNUSED | |2 | | | | | | | | |
|R9 | |IOBS |IO_L16N_VREF_2 |UNUSED | |2 | | | | | | | | |
|R10 | |IOBS |IO_L13N_D10_2 |UNUSED | |2 | | | | | | | | |
|R11 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | |
|R12 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | |
|R13 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | |
|R14 | | |DONE_2 | | | | | | | | | | | |
|R15 | | |GND | | | | | | | | | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

1998
SpecialCasesCheck_par.xrpt Normal file
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SpecialCasesCheck_summary.html
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@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 17:19:45)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/24/2019 - 12:14:34)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>IEEE754Adder.xise</TD>
@@ -13,7 +13,7 @@
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>SpecialCasesCheck</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized</TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
@@ -25,14 +25,14 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.unroutes'>All Signals Completely Routed</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
@@ -43,40 +43,267 @@ No Errors</TD>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
<TD>0 &nbsp;<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>15</TD>
<TD ALIGN=RIGHT>2400</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>15</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
<TD ALIGN=RIGHT>4,800</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>2,400</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>2,400</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O6 output only</TD>
<TD ALIGN=RIGHT>25</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number used as ROM</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Memory</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1,200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>10</TD>
<TD ALIGN=RIGHT>600</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of MUXCYs used</TD>
<TD ALIGN=RIGHT>12</TD>
<TD ALIGN=RIGHT>1,200</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>26</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>26</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4,800</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>66</TD>
<TD ALIGN=RIGHT>132</TD>
<TD ALIGN=RIGHT COLSPAN='2'>50%</TD>
<TD ALIGN=RIGHT>50%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB16BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>12</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of RAMB8BWERs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2/BUFIO2_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFIO2FB/BUFIO2FB_2CLKs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>32</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGMUXs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>16</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DCM/DCM_CLKGENs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ILOGIC2/ISERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of IODELAY2/IODRP2/IODRP2_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of OLOGIC2/OSERDES2s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>200</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BSCANs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFHs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>128</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLLs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFPLL_MCBs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of DSP48A1s</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of ICAPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PCILOGICSEs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PLL_ADVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of PMVs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of STARTUPs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of SUSPEND_SYNCs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>1</TD>
<TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>1.78</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
<TD>0 (Setup: 0, Hold: 0)</TD>
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.unroutes'>All Signals Completely Routed</A></TD>
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
<TD COLSPAN='2'><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><B>&nbsp;</B></TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TABLE>
@@ -84,19 +311,23 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 17:19:45 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 24 12:14:14 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.bld'>Translation Report</A></TD><TD>Current</TD><TD>Sat Aug 24 12:14:17 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Sat Aug 24 12:14:25 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/_xmsgs/map.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Sat Aug 24 12:14:30 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Sat Aug 24 12:14:33 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/_xmsgs/trce.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.bgn'>Bitgen Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 24 10:52:30 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 12:12:57 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/netgen/synthesis/SpecialCasesCheck_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:53:07 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:52:31 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:52:32 2019</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 08/17/2019 - 17:19:45</center>
<br><center><b>Date Generated:</b> 08/24/2019 - 12:14:34</center>
</BODY></HTML>

10
SpecialCasesCheck_summary.xml Normal file
View File

@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="6">
<CmdHistory>
</CmdHistory>
</DesignSummary>

313
SpecialCasesCheck_usage.xml Normal file
View File

@@ -0,0 +1,313 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="6">
<DesignStatistics TimeStamp="Sat Aug 24 12:14:25 2019"><group name="NetStatistics">
<item name="NumNets_Active" rev="3">
<attrib name="value" value="148"/></item>
<item name="NumNets_Gnd" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="3">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="3">
<attrib name="value" value="155"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="3">
<attrib name="value" value="130"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="3">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="3">
<attrib name="value" value="66"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="3">
<attrib name="value" value="66"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="3">
<attrib name="value" value="142"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="3">
<attrib name="value" value="144"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="3">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="3">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="3">
<attrib name="value" value="64"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="3">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="3">
<attrib name="value" value="144"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="3">
<attrib name="value" value="399"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="3">
<attrib name="value" value="123"/></item>
<item name="NumNodesOfType_Gnd_BOUNCEIN" rev="3">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Gnd_HGNDOUT" rev="3">
<attrib name="value" value="3"/></item>
<item name="NumNodesOfType_Gnd_PINBOUNCE" rev="3">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Gnd_REGINPUT" rev="3">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="3">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="SiteStatistics">
<item name="IOB-IOBM" rev="3">
<attrib name="value" value="33"/></item>
<item name="IOB-IOBS" rev="3">
<attrib name="value" value="33"/></item>
<item name="SLICEL-SLICEM" rev="3">
<attrib name="value" value="3"/></item>
<item name="SLICEX-SLICEM" rev="3">
<attrib name="value" value="4"/></item>
</group>
<group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="6">
<attrib name="value" value="66"/></item>
<item name="AGG_IO" rev="6">
<attrib name="value" value="66"/></item>
<item name="AGG_SLICE" rev="6">
<attrib name="value" value="10"/></item>
<item name="NUM_BONDED_IOB" rev="6">
<attrib name="value" value="66"/></item>
<item name="NUM_BSLUTONLY" rev="6">
<attrib name="value" value="26"/></item>
<item name="NUM_BSUSED" rev="6">
<attrib name="value" value="26"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="6">
<attrib name="value" value="1"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="6">
<attrib name="value" value="25"/></item>
<item name="NUM_SLICEL" rev="6">
<attrib name="value" value="3"/></item>
<item name="NUM_SLICEX" rev="6">
<attrib name="value" value="7"/></item>
<item name="NUM_SLICE_CARRY4" rev="6">
<attrib name="value" value="3"/></item>
<item name="NUM_SLICE_CYINIT" rev="6">
<attrib name="value" value="28"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="6">
<attrib name="value" value="10"/></item>
</group>
</DesignStatistics>
<ReportConfigData TimeStamp="Sat Aug 24 10:52:30 2019"><group name="IOB_OUTBUF">
<item name="DRIVEATTRBOX" rev="3">
<attrib name="12" value="2"/></item>
<item name="SLEW" rev="3">
<attrib name="SLOW" value="2"/></item>
<item name="SUSPEND" rev="3">
<attrib name="3STATE" value="2"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Sat Aug 24 10:52:30 2019"><group name="SLICEL">
<item name="A1" rev="3">
<attrib name="value" value="2"/></item>
<item name="A2" rev="3">
<attrib name="value" value="3"/></item>
<item name="A3" rev="3">
<attrib name="value" value="3"/></item>
<item name="A4" rev="3">
<attrib name="value" value="3"/></item>
<item name="A5" rev="3">
<attrib name="value" value="3"/></item>
<item name="A6" rev="3">
<attrib name="value" value="3"/></item>
<item name="AX" rev="3">
<attrib name="value" value="2"/></item>
<item name="B1" rev="3">
<attrib name="value" value="3"/></item>
<item name="B2" rev="3">
<attrib name="value" value="3"/></item>
<item name="B3" rev="3">
<attrib name="value" value="3"/></item>
<item name="B4" rev="3">
<attrib name="value" value="3"/></item>
<item name="B5" rev="3">
<attrib name="value" value="3"/></item>
<item name="B6" rev="3">
<attrib name="value" value="3"/></item>
<item name="BX" rev="3">
<attrib name="value" value="3"/></item>
<item name="C1" rev="3">
<attrib name="value" value="3"/></item>
<item name="C2" rev="3">
<attrib name="value" value="3"/></item>
<item name="C3" rev="3">
<attrib name="value" value="3"/></item>
<item name="C4" rev="3">
<attrib name="value" value="3"/></item>
<item name="C5" rev="3">
<attrib name="value" value="3"/></item>
<item name="C6" rev="3">
<attrib name="value" value="3"/></item>
<item name="CIN" rev="3">
<attrib name="value" value="2"/></item>
<item name="CMUX" rev="3">
<attrib name="value" value="1"/></item>
<item name="COUT" rev="3">
<attrib name="value" value="2"/></item>
<item name="CX" rev="3">
<attrib name="value" value="3"/></item>
<item name="D1" rev="3">
<attrib name="value" value="2"/></item>
<item name="D2" rev="3">
<attrib name="value" value="2"/></item>
<item name="D3" rev="3">
<attrib name="value" value="2"/></item>
<item name="D4" rev="3">
<attrib name="value" value="2"/></item>
<item name="D5" rev="3">
<attrib name="value" value="2"/></item>
<item name="D6" rev="3">
<attrib name="value" value="2"/></item>
<item name="DX" rev="3">
<attrib name="value" value="2"/></item>
</group>
<group name="IOB_OUTBUF">
<item name="IN" rev="3">
<attrib name="value" value="2"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="2"/></item>
</group>
<group name="SLICEX">
<item name="A" rev="3">
<attrib name="value" value="5"/></item>
<item name="A1" rev="3">
<attrib name="value" value="3"/></item>
<item name="A2" rev="3">
<attrib name="value" value="3"/></item>
<item name="A3" rev="3">
<attrib name="value" value="5"/></item>
<item name="A4" rev="3">
<attrib name="value" value="5"/></item>
<item name="A5" rev="3">
<attrib name="value" value="5"/></item>
<item name="A6" rev="3">
<attrib name="value" value="5"/></item>
<item name="B" rev="3">
<attrib name="value" value="2"/></item>
<item name="B2" rev="3">
<attrib name="value" value="1"/></item>
<item name="B3" rev="3">
<attrib name="value" value="1"/></item>
<item name="B4" rev="3">
<attrib name="value" value="2"/></item>
<item name="B5" rev="3">
<attrib name="value" value="2"/></item>
<item name="B6" rev="3">
<attrib name="value" value="2"/></item>
<item name="C" rev="3">
<attrib name="value" value="4"/></item>
<item name="C1" rev="3">
<attrib name="value" value="2"/></item>
<item name="C2" rev="3">
<attrib name="value" value="3"/></item>
<item name="C3" rev="3">
<attrib name="value" value="3"/></item>
<item name="C4" rev="3">
<attrib name="value" value="4"/></item>
<item name="C5" rev="3">
<attrib name="value" value="4"/></item>
<item name="C6" rev="3">
<attrib name="value" value="4"/></item>
<item name="D" rev="3">
<attrib name="value" value="4"/></item>
<item name="D1" rev="3">
<attrib name="value" value="4"/></item>
<item name="D2" rev="3">
<attrib name="value" value="4"/></item>
<item name="D3" rev="3">
<attrib name="value" value="4"/></item>
<item name="D4" rev="3">
<attrib name="value" value="4"/></item>
<item name="D5" rev="3">
<attrib name="value" value="4"/></item>
<item name="D6" rev="3">
<attrib name="value" value="4"/></item>
</group>
<group name="PAD">
<item name="PAD" rev="3">
<attrib name="value" value="66"/></item>
</group>
<group name="IOB_INBUF">
<item name="OUT" rev="3">
<attrib name="value" value="64"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="64"/></item>
</group>
<group name="CARRY4">
<item name="CIN" rev="3">
<attrib name="value" value="2"/></item>
<item name="CO2" rev="3">
<attrib name="value" value="1"/></item>
<item name="CO3" rev="3">
<attrib name="value" value="2"/></item>
<item name="CYINIT" rev="3">
<attrib name="value" value="1"/></item>
<item name="DI0" rev="3">
<attrib name="value" value="3"/></item>
<item name="DI1" rev="3">
<attrib name="value" value="3"/></item>
<item name="DI2" rev="3">
<attrib name="value" value="3"/></item>
<item name="DI3" rev="3">
<attrib name="value" value="2"/></item>
<item name="S0" rev="3">
<attrib name="value" value="3"/></item>
<item name="S1" rev="3">
<attrib name="value" value="3"/></item>
<item name="S2" rev="3">
<attrib name="value" value="3"/></item>
<item name="S3" rev="3">
<attrib name="value" value="2"/></item>
</group>
<group name="LUT5">
<item name="O5" rev="3">
<attrib name="value" value="1"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="3">
<attrib name="value" value="19"/></item>
<item name="A2" rev="3">
<attrib name="value" value="22"/></item>
<item name="A3" rev="3">
<attrib name="value" value="24"/></item>
<item name="A4" rev="3">
<attrib name="value" value="26"/></item>
<item name="A5" rev="3">
<attrib name="value" value="26"/></item>
<item name="A6" rev="3">
<attrib name="value" value="26"/></item>
<item name="O6" rev="3">
<attrib name="value" value="26"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="3">
<attrib name="value" value="64"/></item>
<item name="OUT" rev="3">
<attrib name="value" value="64"/></item>
</group>
<group name="IOB">
<item name="I" rev="3">
<attrib name="value" value="64"/></item>
<item name="O" rev="3">
<attrib name="value" value="2"/></item>
<item name="PAD" rev="3">
<attrib name="value" value="66"/></item>
</group>
<group name="HARD1">
<item name="1" rev="3">
<attrib name="value" value="1"/></item>
</group>
</ReportPinData>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>

65
SpecialCasesCheck_xst.xrpt
View File

@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Aug 17 17:19:23 2019">
<application stringID="Xst" timeStamp="Sat Aug 24 12:14:10 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@@ -16,7 +16,7 @@
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
@@ -24,32 +24,40 @@
</row>
<row stringID="row" value="3">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/ise/bin"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/Luca/bin"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="LMC_HOME"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="6">
<row stringID="row" value="5">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="OracleServer"/>
<item stringID="User_EnvOsrelease" value="Oracle Linux Server release 6.4"/>
<item stringID="User_EnvOsname" value="CentOS"/>
<item stringID="User_EnvOsrelease" value="CentOS release 6.10 (Final)"/>
</item>
<item stringID="User_EnvHost" value="localhost.localdomain"/>
<item stringID="User_EnvHost" value="Xilinx"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz"/>
<item stringID="speed" value="2394.454 MHz"/>
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="1">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="2">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="3">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
</table>
</section>
@@ -105,7 +113,16 @@
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_XORS" value="2">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_XORS" value="2">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
@@ -117,12 +134,14 @@
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="16">
<item dataType="int" stringID="XST_BELS" value="39">
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_LUT3" value="2"/>
<item dataType="int" stringID="XST_LUT4" value="2"/>
<item dataType="int" stringID="XST_LUT4" value="3"/>
<item dataType="int" stringID="XST_LUT5" value="2"/>
<item dataType="int" stringID="XST_LUT6" value="9"/>
<item dataType="int" stringID="XST_LUT6" value="19"/>
<item dataType="int" stringID="XST_MUXCY" value="11"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
<item dataType="int" stringID="XST_IBUF" value="64"/>
@@ -132,12 +151,12 @@
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="xa6slx4csg225-3"/>
<item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="15"/>
<item AVAILABLE="2400" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="15"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="15"/>
<item AVAILABLE="15" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="15"/>
<item AVAILABLE="15" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="15" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
<item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="26"/>
<item AVAILABLE="2400" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="26"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="26"/>
<item AVAILABLE="26" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="26"/>
<item AVAILABLE="26" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
<item AVAILABLE="26" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="0"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="66"/>
<item AVAILABLE="132" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>

165
SpecialCasesTest.vhd Normal file
View File

@@ -0,0 +1,165 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SpecialCasesTest IS
END SpecialCasesTest;
ARCHITECTURE behavior OF SpecialCasesTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SpecialCasesCheck
PORT(
X : IN std_logic_vector(31 downto 0);
Y : IN std_logic_vector(31 downto 0);
isNaN : OUT std_logic;
isZero : OUT std_logic
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(31 downto 0) := (others => '0');
signal Y : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal isNaN : std_logic;
signal isZero : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock : std_logic;
signal expectedNaN : std_logic;
signal expectedZero : std_logic;
signal error : std_logic;
constant clock_period : time := 1 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SpecialCasesCheck PORT MAP (
X => X,
Y => Y,
isNaN => isNaN,
isZero => isZero
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
test_process :process
begin
X <= "01111111111111111111111111111111"; -- NaN
Y <= "01111111111111111111111111111111"; -- NaN
expectedNaN <= '1';
expectedZero <= '0';
wait for clock_period;
X <= "01111111111111111111111111111111"; -- NaN
Y <= "01000101100101100111100101001100"; -- 4815.162342
expectedNaN <= '1';
expectedZero <= '0';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "01111111111111111111111111111111"; -- NaN
expectedNaN <= '1';
expectedZero <= '0';
wait for clock_period;
X <= "01111111111111111111111111111111"; -- NaN
Y <= "01111111100000000000000000000000"; -- +Inf
expectedNaN <= '1';
expectedZero <= '0';
wait for clock_period;
X <= "01111111100000000000000000000000"; -- +Inf
Y <= "01111111100000000000000000000000"; -- +Inf
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "01111111100000000000000000000000"; -- +Inf
Y <= "11111111100000000000000000000000"; -- -Inf
expectedNaN <= '1';
expectedZero <= '1';
wait for clock_period;
X <= "11111111100000000000000000000000"; -- -Inf
Y <= "01111111100000000000000000000000"; -- +Inf
expectedNaN <= '1';
expectedZero <= '1';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "01111111100000000000000000000000"; -- +Inf
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "11111111100000000000000000000000"; -- -Inf
Y <= "01000101100101100111100101001100"; -- 4815.162342
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "01000101100101100111100101001100"; -- 4815.162342
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "01111101001101101011100011111101"; -- 1.518e+37
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "11000101100101100111100101001100"; -- -4815.162342
expectedNaN <= '0';
expectedZero <= '1';
wait for clock_period;
X <= "11000101100101100111100101001100"; -- -4815.162342
Y <= "01000101100101100111100101001100"; -- 4815.162342
expectedNaN <= '0';
expectedZero <= '1';
wait for clock_period;
X <= "01111101001101101011100011111101"; -- 1.518e+37
Y <= "11000101100101100111100101001100"; -- -4815.162342
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "11000101100101100111100101001100"; -- -4815.162342
Y <= "11000101100101100111100101001100"; -- -4815.162342
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "11000101100101100111100101001100"; -- -4815.162342
Y <= "11111101001101101011100011111101"; -- -1.518e+37
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "01000101100101100111100101001100"; -- 4815.162342
Y <= "01111101001101101011100011111101"; -- 1.518e+37
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "00000000000000000000000000000000"; -- 0
Y <= "00000000000000000000000000000000"; -- 0
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
X <= "00000000000000000000000000000000"; -- +0
Y <= "10000000000000000000000000000000"; -- -0
expectedNaN <= '0';
expectedZero <= '1';
wait for clock_period;
X <= "00000000000000000000000000000000"; -- 0
Y <= "01000101100101100111100101001100"; -- 4815.162342
expectedNaN <= '0';
expectedZero <= '0';
wait for clock_period;
end process;
error <= (expectedNaN xor isNaN) or (expectedZero xor isZero);
END;

6
SpecialCasesTest_beh.prj Normal file
View File

@@ -0,0 +1,6 @@
vhdl work "TypeCheck.vhd"
vhdl work "EqualCheck.vhd"
vhdl work "ZeroCheck.vhd"
vhdl work "NaNCheck.vhd"
vhdl work "SpecialCasesCheck.vhd"
vhdl work "SpecialCasesTest.vhd"

BIN
SpecialCasesTest_isim_beh.exe Executable file
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Binary file not shown.

BIN
SpecialCasesTest_isim_beh.wdb Normal file
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Binary file not shown.

6
SpecialCasesTest_stx_beh.prj Normal file
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@@ -0,0 +1,6 @@
vhdl isim_temp "TypeCheck.vhd"
vhdl isim_temp "EqualCheck.vhd"
vhdl isim_temp "ZeroCheck.vhd"
vhdl isim_temp "NaNCheck.vhd"
vhdl isim_temp "SpecialCasesCheck.vhd"
vhdl isim_temp "SpecialCasesTest.vhd"

40
ZeroCheck.vhd Normal file
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@@ -0,0 +1,40 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ZeroCheck is
port(
X, Y: in std_logic_vector(31 downto 0);
isZero: out std_logic
);
end ZeroCheck;
architecture ZeroCheckArch of ZeroCheck is
component EqualCheck is
generic( BITCOUNT: integer := 8 );
port(
X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
isEqual: out std_logic
);
end component;
signal xSign: std_logic;
signal ySign: std_logic;
signal xAbs: std_logic_vector(30 downto 0);
signal yAbs: std_logic_vector(30 downto 0);
signal isSameAbsValue: std_logic;
signal isSameSign: std_logic;
begin
xSign <= X(31);
ySign <= Y(31);
xAbs <= X(30 downto 0);
yAbs <= Y(30 downto 0);
isSameSign <= xSign xnor ySign;
AbsCheck: EqualCheck
generic map ( BITCOUNT => 31 )
port map (X => xAbs, Y => yAbs, isEqual => isSameAbsValue);
isZero <= (not isSameSign) and isSameAbsValue;
end ZeroCheckArch;

2
_ngo/netlist.lst
View File

@@ -1,2 +1,2 @@
/home/Luca/ISE/IEEE754Adder/TypeCheck.ngc 1566052852
/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc 1566641654
OK

9
_xmsgs/bitgen.xmsgs Normal file
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@@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

27
_xmsgs/map.xmsgs
View File

@@ -5,23 +5,20 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N&lt;31&gt;</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">29</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N&lt;30&gt;,
N&lt;29&gt;,
N&lt;28&gt;,
N&lt;27&gt;,
N&lt;26&gt;</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">100.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">-40.000</arg> to <arg fmt="%0.3f" index="3">100.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
</msg>
</messages>

12
_xmsgs/netgen.xmsgs Normal file
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@@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="NetListWriters" num="635" delta="new" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> library for correct compilation and simulation.
</msg>
</messages>

3
_xmsgs/par.xmsgs
View File

@@ -8,5 +8,8 @@
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
<msg type="info" file="Par" num="459" delta="old" >The Clock Report is not displayed in the non timing-driven mode.
</msg>
</messages>

2
_xmsgs/pn_parser.xmsgs
View File

@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd&quot; into library work</arg>
</msg>
</messages>

4
_xmsgs/trce.xmsgs
View File

@@ -13,9 +13,5 @@
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
</messages>

2
_xmsgs/xst.xmsgs
View File

@@ -5,7 +5,7 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">N&lt;31:31&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">N&lt;31:31&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
</messages>

2
equalCheck.cmd_log Normal file
View File

@@ -0,0 +1,2 @@
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/equalCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/equalCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/equalCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/equalCheck.syr"

1
equalCheck.lso Normal file
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@@ -0,0 +1 @@
work

3
equalCheck.ngc Normal file
View File

@@ -0,0 +1,3 @@
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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vhdl work "equalCheck.vhd"

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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
-->
Reading design: equalCheck.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "equalCheck.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "equalCheck"
Output Format : NGC
Target Device : xa6slx4-3-csg225
---- Source Options
Top Module Name : equalCheck
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd" into library work
Parsing entity <equalCheck>.
Parsing architecture <equalCheckArch> of entity <equalcheck>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <equalCheck> (architecture <equalCheckArch>) with generics from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <equalCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/equalCheck.vhd".
BITCOUNT = 8
Summary:
Unit <equalCheck> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Xors : 1
8-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Xors : 1
8-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <equalCheck> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block equalCheck, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : equalCheck.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 4
# LUT5 : 1
# LUT6 : 3
# IO Buffers : 17
# IBUF : 16
# OBUF : 1
Device utilization summary:
---------------------------
Selected Device : xa6slx4csg225-3
Slice Logic Utilization:
Number of Slice LUTs: 4 out of 2400 0%
Number used as Logic: 4 out of 2400 0%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 4
Number with an unused Flip Flop: 4 out of 4 100%
Number with an unused LUT: 0 out of 4 0%
Number of fully used LUT-FF pairs: 0 out of 4 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 17
Number of bonded IOBs: 17 out of 132 12%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.658ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 20 / 1
-------------------------------------------------------------------------
Delay: 7.658ns (Levels of Logic = 5)
Source: X<7> (PAD)
Destination: isEqual (PAD)
Data Path: X<7> to isEqual
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.944 X_7_IBUF (X_7_IBUF)
LUT6:I0->O 1 0.203 0.924 isEqual<0>4 (isEqual<0>3)
LUT5:I0->O 1 0.203 0.808 isEqual<0>5_SW0 (N2)
LUT6:I3->O 1 0.205 0.579 isEqual<0>5 (isEqual_OBUF)
OBUF:I->O 2.571 isEqual_OBUF (isEqual)
----------------------------------------
Total 7.658ns (4.404ns logic, 3.254ns route)
(57.5% logic, 42.5% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.71 secs
-->
Total memory usage is 474280 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity EqualCheck is
generic( BITCOUNT: integer := 8 );
port(
X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
isEqual: out std_logic
);
end EqualCheck;
architecture EqualCheckArch of EqualCheck is
signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
begin
compVec <= X xor Y;
res_compute: process (compVec)
variable res_tmp: std_logic;
begin
res_tmp := '0';
for i in compVec'range loop
res_tmp := res_tmp or compVec(i);
end loop;
isEqual <= res_tmp;
end process;
end EqualCheckArch;

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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn equalCheck.prj
-ofn equalCheck
-ofmt NGC
-p xa6slx4-3-csg225
-top equalCheck
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 32
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>equalCheck.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>equalCheck</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xa6slx4-3-csg225</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>equalCheck</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>32</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>Host</td>
<td>Xilinx</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Name</td>
<td>CentOS</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>CentOS release 6.10 (Final)</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
</TABLE>
</BODY> </HTML>

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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/24/2019 - 12:12:36)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>IEEE754Adder.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>equalCheck</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Placed and Routed</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xa6slx4-3csg225</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/equalCheck_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>2400</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>132</TD>
<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/equalCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 24 10:22:02 2019</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 12:11:57 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/netgen/synthesis/SpecialCasesCheck_synthesis.nlf'>Post-Synthesis Simulation Model Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:53:07 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:52:31 2019</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Sat Aug 24 10:52:32 2019</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 08/24/2019 - 12:12:36</center>
</BODY></HTML>

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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Sat Aug 24 10:21:59 2019">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="PATH"/>
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<section stringID="XST_">
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30
fuse.log Normal file
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj work.SpecialCasesTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94420 KB
Fuse CPU Usage: 980 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture typecheckarch of entity TypeCheck [typecheck_default]
Compiling architecture nancheckarch of entity NaNCheck [nancheck_default]
Compiling architecture equalcheckarch of entity EqualCheck [\EqualCheck(31)\]
Compiling architecture zerocheckarch of entity ZeroCheck [zerocheck_default]
Compiling architecture specialcasescheckarch of entity SpecialCasesCheck [specialcasescheck_default]
Compiling architecture behavior of entity specialcasestest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 13 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe
Fuse Memory Usage: 658120 KB
Fuse CPU Usage: 1000 ms
GCC CPU Usage: 280 ms

9
fuse.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

1
fuseRelaunch.cmd Normal file
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@@ -0,0 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj" "work.SpecialCasesTest"

82
iseconfig/IEEE754Adder.projectmgr
View File

@@ -9,41 +9,40 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd)</SelectedItem>
<SelectedItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000222000000020000000000000000000000000200000064ffffffff000000810000000300000002000002220000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd)</CurrentItem>
<CurrentItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
<ClosedNode>Design Utilities/Compile HDL Simulation Libraries</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>View RTL Schematic</SelectedItem>
<SelectedItem>Regenerate All Cores</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000160000000010000000100000000000000000000000064ffffffff000000810000000000000001000001600000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>View RTL Schematic</CurrentItem>
<CurrentItem>Regenerate All Cores</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<SelectedItems>
<SelectedItem>SpecialCasesTest.vhd</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028a000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b600000001000000000000005d0000000100000000000000840000000100000000000000f30000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000039f000000040101000100000000000000000000000064ffffffff000000810000000000000004000000510000000100000000000000290000000100000000000000840000000100000000000002a10000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>SpecialCasesCheck.vhd</CurrentItem>
<CurrentItem>SpecialCasesTest.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
@@ -57,20 +56,65 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate Post-Place &amp; Route Static Timing</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem>View RTL Schematic</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem>View RTL Schematic</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>SpecialCasesTest - behavior (/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd)</SelectedItem>
</SelectedItems>
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<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>SpecialCasesTest - behavior (/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
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<ClosedNodesVersion>1</ClosedNodesVersion>
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<SelectedItems>
<SelectedItem>Design Utilities</SelectedItem>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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10
iseconfig/SpecialCasesCheck.xreport
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@@ -1,12 +1,12 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-08-17T16:51:16</DateModified>
<DateModified>2019-08-24T12:13:27</DateModified>
<ModuleName>SpecialCasesCheck</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/ise/gianni/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/ise/gianni/IEEE754Adder/</ImplementationReportsDirectory>
<DateInitialized>2019-08-17T15:26:24</DateInitialized>
<SummaryTimeStamp>2019-08-24T10:53:09</SummaryTimeStamp>
<SavedFilePath>/home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/Luca/ISE/IEEE754Adder/</ImplementationReportsDirectory>
<DateInitialized>2019-08-24T10:27:23</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>

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isim.cmd Normal file
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onerror {resume}
wave add /
run 1000 ns;

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isim.log Normal file
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ISim log file
Running: /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

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isim/NaNCheck_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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isim/NaNCheck_isim_beh.exe.sim/NaNCheck_isim_beh.exe Executable file
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0
isim/NaNCheck_isim_beh.exe.sim/isimcrash.log Normal file
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isim/NaNCheck_isim_beh.exe.sim/isimkernel.log Normal file
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Command line:
NaNCheck_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 39524
Sat Aug 24 12:14:44 2019
Elaboration Time: 0.02 sec
Current Memory Usage: 195.346 Meg
Total Signals : 23
Total Nets : 137
Total Signal Drivers : 15
Total Blocks : 4
Total Primitive Blocks : 3
Total Processes : 15
Total Traceable Variables : 8
Total Scalar Nets and Variables : 497
Total Line Count : 27
Total Simulation Time: 0.04 sec
Current Memory Usage: 272.945 Meg
Sat Aug 24 12:14:54 2019

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isim/NaNCheck_isim_beh.exe.sim/netId.dat Normal file
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isim/NaNCheck_isim_beh.exe.sim/tmp_save/_1 Normal file
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isim/NaNCheck_isim_beh.exe.sim/work/NaNCheck_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0557987184_1272247069_init();
work_a_4078426953_2628201599_init();
xsi_register_tops("work_a_4078426953_2628201599");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/NaNCheck_isim_beh.exe.sim/work/NaNCheck_isim_beh.exe_main.lin64.o Normal file
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isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.c Normal file
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@@ -0,0 +1,368 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0557987184_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7603);
*((int *)t1) = 7;
t2 = (t0 + 7607);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7603);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7603);
t3 = *((int *)t1);
t2 = (t0 + 7607);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7603);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7611);
*((int *)t1) = 22;
t2 = (t0 + 7615);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7611);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7611);
t3 = *((int *)t1);
t2 = (t0 + 7615);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7611);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0557987184_1272247069_init()
{
static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5};
xsi_register_didat("work_a_0557987184_1272247069", "isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat");
xsi_register_executes(pe);
}

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isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat Normal file
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isim/NaNCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.lin64.o Normal file
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isim/NaNCheck_isim_beh.exe.sim/work/a_4078426953_2628201599.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_4078426953_2628201599_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(32, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4392);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4280);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4078426953_2628201599_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4456);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4296);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4078426953_2628201599_p_2(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
char *t12;
unsigned char t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
unsigned char t19;
char *t20;
unsigned char t21;
char *t22;
unsigned char t23;
unsigned char t24;
unsigned char t25;
char *t26;
unsigned char t27;
unsigned char t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
LAB0: xsi_set_current_line(35, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1672U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1832U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t1 = (t0 + 2152U);
t12 = *((char **)t1);
t13 = *((unsigned char *)t12);
t14 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t11, t13);
t1 = (t0 + 2312U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t17);
t19 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t18);
t1 = (t0 + 1672U);
t20 = *((char **)t1);
t21 = *((unsigned char *)t20);
t1 = (t0 + 1832U);
t22 = *((char **)t1);
t23 = *((unsigned char *)t22);
t24 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t23);
t25 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t24);
t1 = (t0 + 2152U);
t26 = *((char **)t1);
t27 = *((unsigned char *)t26);
t28 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t25, t27);
t1 = (t0 + 2312U);
t29 = *((char **)t1);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t28, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t19, t31);
t1 = (t0 + 4520);
t33 = (t1 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
*((unsigned char *)t36) = t32;
xsi_driver_first_trans_fast_port(t1);
LAB2: t37 = (t0 + 4312);
*((int *)t37) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_4078426953_2628201599_init()
{
static char *pe[] = {(void *)work_a_4078426953_2628201599_p_0,(void *)work_a_4078426953_2628201599_p_1,(void *)work_a_4078426953_2628201599_p_2};
xsi_register_didat("work_a_4078426953_2628201599", "isim/NaNCheck_isim_beh.exe.sim/work/a_4078426953_2628201599.didat");
xsi_register_executes(pe);
}

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Command line:
SpecialCasesTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 47173
Sat Aug 24 12:20:10 2019
Elaboration Time: 0.01 sec
Current Memory Usage: 195.359 Meg
Total Signals : 48
Total Nets : 239
Total Signal Drivers : 29
Total Blocks : 8
Total Primitive Blocks : 4
Total Processes : 26
Total Traceable Variables : 10
Total Scalar Nets and Variables : 601
Total Line Count : 143
Total Simulation Time: 0.04 sec
Current Memory Usage: 272.957 Meg
Sat Aug 24 14:38:35 2019

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isim/SpecialCasesTest_isim_beh.exe.sim/work/SpecialCasesTest_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0557987184_1272247069_init();
work_a_3914402253_2628201599_init();
work_a_2347761600_1146481140_init();
work_a_1540508602_4151211736_init();
work_a_2912948712_3395701438_init();
work_a_4189535622_2372691052_init();
xsi_register_tops("work_a_4189535622_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/SpecialCasesTest_isim_beh.exe.sim/work/a_0557987184_1272247069.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0557987184_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7603);
*((int *)t1) = 7;
t2 = (t0 + 7607);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7603);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7603);
t3 = *((int *)t1);
t2 = (t0 + 7607);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7603);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7611);
*((int *)t1) = 22;
t2 = (t0 + 7615);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7611);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7611);
t3 = *((int *)t1);
t2 = (t0 + 7615);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7611);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0557987184_1272247069_init()
{
static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5};
xsi_register_didat("work_a_0557987184_1272247069", "isim/SpecialCasesTest_isim_beh.exe.sim/work/a_0557987184_1272247069.didat");
xsi_register_executes(pe);
}

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isim/SpecialCasesTest_isim_beh.exe.sim/work/a_0557987184_1272247069.didat Normal file
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isim/SpecialCasesTest_isim_beh.exe.sim/work/a_0557987184_1272247069.lin64.o Normal file
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