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Completato check casi speciali + test

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This commit is contained in:
Luca Cuzzocrea
2019-08-24 14:39:01 +02:00
parent cd358fae35
commit c6ef95462a
143 changed files with 21122 additions and 224 deletions
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182
IEEE754Adder.gise
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@@ -22,18 +22,52 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="IEEE754Adder.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="NaNCheck_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="NaNCheck_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="SpecialCasesCheck.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="SpecialCasesCheck.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="SpecialCasesCheck.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="SpecialCasesCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="SpecialCasesCheck.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="SpecialCasesCheck.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="SpecialCasesCheck.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="SpecialCasesCheck.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="SpecialCasesCheck.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="SpecialCasesCheck.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="SpecialCasesCheck.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="SpecialCasesCheck.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="SpecialCasesCheck.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="SpecialCasesCheck.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="SpecialCasesCheck.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="SpecialCasesCheck.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="SpecialCasesCheck.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="SpecialCasesCheck.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="SpecialCasesCheck.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="SpecialCasesCheck.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="SpecialCasesCheck.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_envsettings.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="SpecialCasesCheck_fpga_editor.log"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SpecialCasesCheck_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="SpecialCasesCheck_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="SpecialCasesCheck_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="SpecialCasesCheck_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="SpecialCasesCheck_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="SpecialCasesCheck_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="SpecialCasesCheck_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="SpecialCasesCheck_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="SpecialCasesCheck_usage.xml"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesTest_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SpecialCasesTest_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="SpecialCasesTest_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="SpecialCasesTest_stx_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="TypeCheck.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="TypeCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="TypeCheck.lso"/>
@@ -59,7 +93,6 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="TypeCheck_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="TypeCheck_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="TypeCheck_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="TypeCheck_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_par.xrpt"/>
@@ -68,12 +101,34 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="TypeCheck_vhdl.prj"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="TypeCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="equalCheck.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="equalCheck.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="equalCheck.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="equalCheck.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="equalCheck.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="equalCheck.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="equalCheck.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="equalCheck.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="equalCheck_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="equalCheck_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="equalCheck_xst.xrpt"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="netgen"/>
<file xil_pn:fileType="FILE_NETGEN_REPORT" xil_pn:name="netgen/synthesis/SpecialCasesCheck_synthesis.nlf"/>
<file xil_pn:fileType="FILE_VHDL" xil_pn:name="netgen/synthesis/SpecialCasesCheck_synthesis.vhd"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
@@ -83,38 +138,97 @@
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641680" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1566641680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566642007" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="EqualCheck.vhd"/>
<outfile xil_pn:name="NaNCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesTest.vhd"/>
<outfile xil_pn:name="TypeCheck.vhd"/>
<outfile xil_pn:name="ZeroCheck.vhd"/>
</transform>
<transform xil_pn:end_ts="1566641747" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2553664997009849434" xil_pn:start_ts="1566641747">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8700953375414271688" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566641747" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4514528137675365326" xil_pn:start_ts="1566641747">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641680" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8552960292560004185" xil_pn:start_ts="1566641680">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566642007" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="EqualCheck.vhd"/>
<outfile xil_pn:name="NaNCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesCheck.vhd"/>
<outfile xil_pn:name="SpecialCasesTest.vhd"/>
<outfile xil_pn:name="TypeCheck.vhd"/>
<outfile xil_pn:name="ZeroCheck.vhd"/>
</transform>
<transform xil_pn:end_ts="1566642009" xil_pn:in_ck="-4971464007376685235" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="5476011783414369773" xil_pn:start_ts="1566642007">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesTest_beh.prj"/>
<outfile xil_pn:name="SpecialCasesTest_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1566642009" xil_pn:in_ck="-7882590952032427895" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8388436521910439718" xil_pn:start_ts="1566642009">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesTest_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="4779560239316253549" xil_pn:start_ts="1566052458">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-135021957620618676" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-1647368633314702702" xil_pn:start_ts="1566059978">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8552960292560004185" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566062385" xil_pn:in_ck="-3915287225243783751" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566062357">
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2391194399288376768" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="6075245583379680512" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641648" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7265458583967929315" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566641654" xil_pn:in_ck="7192749262906653965" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566641648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="SpecialCasesCheck.lso"/>
<outfile xil_pn:name="SpecialCasesCheck.ngc"/>
<outfile xil_pn:name="SpecialCasesCheck.ngr"/>
@@ -122,35 +236,57 @@
<outfile xil_pn:name="SpecialCasesCheck.stx"/>
<outfile xil_pn:name="SpecialCasesCheck.syr"/>
<outfile xil_pn:name="SpecialCasesCheck.xst"/>
<outfile xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
<outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
<outfile xil_pn:name="TypeCheck.ngr"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1566062226" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566062226">
<transform xil_pn:end_ts="1566641654" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566641654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
<status xil_pn:value="AbortedRun"/>
<transform xil_pn:end_ts="1566641658" xil_pn:in_ck="-4436930658892351530" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1077053878783850095" xil_pn:start_ts="1566641654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="TypeCheck.bld"/>
<outfile xil_pn:name="TypeCheck.ngd"/>
<outfile xil_pn:name="TypeCheck_ngdbuild.xrpt"/>
<outfile xil_pn:name="SpecialCasesCheck.bld"/>
<outfile xil_pn:name="SpecialCasesCheck.ngd"/>
<outfile xil_pn:name="SpecialCasesCheck_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1566052863" xil_pn:in_ck="-1179315243053685469" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1566052862">
<transform xil_pn:end_ts="1566641665" xil_pn:in_ck="-238049757476689252" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="6289270943427689258" xil_pn:start_ts="1566641658">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="TypeCheck.twr"/>
<outfile xil_pn:name="TypeCheck.twx"/>
<outfile xil_pn:name="SpecialCasesCheck.pcf"/>
<outfile xil_pn:name="SpecialCasesCheck_map.map"/>
<outfile xil_pn:name="SpecialCasesCheck_map.mrp"/>
<outfile xil_pn:name="SpecialCasesCheck_map.ncd"/>
<outfile xil_pn:name="SpecialCasesCheck_map.ngm"/>
<outfile xil_pn:name="SpecialCasesCheck_map.xrpt"/>
<outfile xil_pn:name="SpecialCasesCheck_summary.xml"/>
<outfile xil_pn:name="SpecialCasesCheck_usage.xml"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1566641674" xil_pn:in_ck="7133440223257255534" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7367957561374022844" xil_pn:start_ts="1566641665">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="SpecialCasesCheck.ncd"/>
<outfile xil_pn:name="SpecialCasesCheck.pad"/>
<outfile xil_pn:name="SpecialCasesCheck.par"/>
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