lucacuzzocrea/IEEE754Adder
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Luca Cuzzocrea
2019-08-28 21:50:05 +02:00
parent f8b3061b00
commit a91e1252d0
80 changed files with 4236 additions and 50 deletions
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planAhead_run_1/IEEE754Adder.ppr Normal file
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<?xml version="1.0"?>
<!--Product Version: PlanAhead v14.7 (64-bit)-->
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="45689c7b25ae425b84c8ab3f166c9430"/>
<Option Name="Part" Val="xa6slx4csg225-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="TargetLanguage" Val="Verilog"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="All"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>