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This commit is contained in:
Luca Cuzzocrea
2019-08-28 21:50:05 +02:00
parent f8b3061b00
commit a91e1252d0
80 changed files with 4236 additions and 50 deletions
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1762
planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif vendored Normal file
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planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../SpecialCasesCheck.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../SpecialCasesCheck.ucf"/>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>

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planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg Normal file
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<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>

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planAhead_run_1/IEEE754Adder.data/runs/runs.xml Normal file
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<?xml version="1.0"?>
<Runs Version="1" Minor="8">
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xa6slx4csg225-3" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
</Runs>

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planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</DARoots>

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planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="EDIFSrcs"/>
<File Path="$PPRDIR/../SpecialCasesCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../equalCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TypeCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="GateLvl"/>
<Option Name="GateLvlMode" Val="EDIF"/>
<Option Name="TopFile" Val="$PPRDIR/../SpecialCasesCheck.ngc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</DARoots>

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planAhead_run_1/IEEE754Adder.data/wt/java_command_handlers.wdf Normal file
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version:1
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:35:00:00
eof:3762079013

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planAhead_run_1/IEEE754Adder.data/wt/project.wpc Normal file
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version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
6d6f64655f636f756e7465727c4953454d6f6465:1
eof:

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planAhead_run_1/IEEE754Adder.data/wt/webtalk_pa.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Aug 24 14:52:23 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="e7a017e01966464abdfa199c35ad33a2" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="GateLvl" type="DesignMode"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="ZoomIn" value="5" type="JavaHandler"/>
</item>
<item name="Other">
<property name="GuiMode" value="0" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="1" type="ISEMode"/>
</item>
</section>
</application>
</document>

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planAhead_run_1/IEEE754Adder.ppr Normal file
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<?xml version="1.0"?>
<!--Product Version: PlanAhead v14.7 (64-bit)-->
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="45689c7b25ae425b84c8ab3f166c9430"/>
<Option Name="Part" Val="xa6slx4csg225-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="TargetLanguage" Val="Verilog"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="All"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>

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planAhead_run_1/planAhead.jou Normal file
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#-----------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
# Start of session at: Sat Aug 24 14:51:32 2019
# Process ID: 7025
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl

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planAhead_run_1/planAhead.log Normal file
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#-----------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
# Start of session at: Sat Aug 24 14:51:32 2019
# Process ID: 7025
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
# set srcset [get_property srcset [current_run -impl]]
# set_property design_mode GateLvl $srcset
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xa6slx4csg225-3
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design SpecialCasesCheck.ngc ...
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SpecialCasesCheck.edif ...
ngc2edif: Total memory usage is 103004 kilobytes
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Phase 0 | Netlist Checksum: 684e9dfa
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-671] Placed 103 instances
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
# }
exit
ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
(See /home/Luca/ISE/IEEE754Adder/planAhead_pid7025.debug)
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
INFO: [Common 17-83] Releasing license: PlanAhead

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planAhead_run_1/planAhead_run.log Normal file
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****** PlanAhead v14.7 (64-bit)
**** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
# set srcset [get_property srcset [current_run -impl]]
# set_property design_mode GateLvl $srcset
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xa6slx4csg225-3
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design SpecialCasesCheck.ngc ...
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SpecialCasesCheck.edif ...
ngc2edif: Total memory usage is 103004 kilobytes
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Phase 0 | Netlist Checksum: 684e9dfa
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-671] Placed 103 instances
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
# }
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
INFO: [Common 17-83] Releasing license: PlanAhead