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TypeCheck_map.map

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+Release 14.7 Map P.20131013 (lin64)
+Xilinx Map Application Log File for Design 'TypeCheck'
+
+Design Information
+------------------
+Command Line   : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c
+100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf 
+Target Device  : xc3s50
+Target Package : pq208
+Target Speed   : -5
+Mapper Version : spartan3 -- $Revision: 1.55 $
+Mapped Date    : Sat Aug 17 16:40:57 2019
+
+Mapping design into LUTs...
+Running directed packing...
+Running delay-based LUT packing...
+Running related packing...
+Updating timing models...
+
+Design Summary
+--------------
+
+Design Summary:
+Number of errors:      0
+Number of warnings:    0
+Logic Utilization:
+  Number of 4 input LUTs:                 4 out of   1,536    1%
+Logic Distribution:
+  Number of occupied Slices:              2 out of     768    1%
+    Number of Slices containing only related logic:       2 out of       2 100%
+    Number of Slices containing unrelated logic:          0 out of       2   0%
+      *See NOTES below for an explanation of the effects of unrelated logic.
+  Total Number of 4 input LUTs:           4 out of   1,536    1%
+  Number of bonded IOBs:                  4 out of     124    3%
+
+Average Fanout of Non-Clock Nets:                1.67
+
+Peak Memory Usage:  615 MB
+Total REAL time to MAP completion:  1 secs 
+Total CPU time to MAP completion:   1 secs 
+
+NOTES:
+
+   Related logic is defined as being logic that shares connectivity - e.g. two
+   LUTs are "related" if they share common inputs.  When assembling slices,
+   Map gives priority to combine logic that is related.  Doing so results in
+   the best timing performance.
+
+   Unrelated logic shares no connectivity.  Map will only begin packing
+   unrelated logic into a slice once 99% of the slices are occupied through
+   related logic packing.
+
+   Note that once logic distribution reaches the 99% level through related
+   logic packing, this does not mean the device is completely utilized.
+   Unrelated logic packing will then begin, continuing until all usable LUTs
+   and FFs are occupied.  Depending on your timing budget, increased levels of
+   unrelated logic packing may adversely affect the overall timing performance
+   of your design.
+
+Mapping completed.
+See MAP report file "TypeCheck_map.mrp" for details.