Initial commit

TypeCheck.par

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+Release 14.7 par P.20131013 (lin64)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Xilinx::  Sat Aug 17 16:41:01 2019
+
+par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd
+TypeCheck.pcf 
+
+
+Constraints file: TypeCheck.pcf.
+Loading device for application Rf_Device from file '3s50.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+   "TypeCheck" is an NCD, version 3.2, device xc3s50, package pq208, speed -5
+
+Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
+Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
+
+INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
+   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
+   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
+   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
+   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".
+
+Device speed data version:  "PRODUCTION 1.39 2013-10-13".
+
+
+Device Utilization Summary:
+
+   Number of External IOBs                   4 out of 124     3%
+      Number of LOCed IOBs                   0 out of 4       0%
+
+   Number of Slices                          2 out of 768     1%
+      Number of SLICEMs                      0 out of 384     0%
+
+
+
+Overall effort level (-ol):   High 
+Placer effort level (-pl):    High 
+Placer cost table entry (-t): 1
+Router effort level (-rl):    High 
+
+Starting initial Timing Analysis.  REAL time: 0 secs 
+Finished initial Timing Analysis.  REAL time: 0 secs 
+
+
+Starting Placer
+Total REAL time at the beginning of Placer: 0 secs 
+Total CPU  time at the beginning of Placer: 0 secs 
+
+Phase 1.1  Initial Placement Analysis
+Phase 1.1  Initial Placement Analysis (Checksum:14) REAL time: 0 secs 
+
+Phase 2.7  Design Feasibility Check
+Phase 2.7  Design Feasibility Check (Checksum:14) REAL time: 0 secs 
+
+Phase 3.31  Local Placement Optimization
+Phase 3.31  Local Placement Optimization (Checksum:14) REAL time: 0 secs 
+
+Phase 4.2  Initial Clock and IO Placement
+...
+Phase 4.2  Initial Clock and IO Placement (Checksum:14) REAL time: 0 secs 
+
+Phase 5.36  Local Placement Optimization
+Phase 5.36  Local Placement Optimization (Checksum:14) REAL time: 0 secs 
+
+Phase 6.3  Local Placement Optimization
+...
+Phase 6.3  Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs 
+
+Phase 7.5  Local Placement Optimization
+Phase 7.5  Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs 
+
+Phase 8.8  Global Placement
+..
+Phase 8.8  Global Placement (Checksum:78ce46) REAL time: 0 secs 
+
+Phase 9.5  Local Placement Optimization
+Phase 9.5  Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs 
+
+Phase 10.18  Placement Optimization
+Phase 10.18  Placement Optimization (Checksum:78ce46) REAL time: 0 secs 
+
+Phase 11.5  Local Placement Optimization
+Phase 11.5  Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs 
+
+Total REAL time to Placer completion: 0 secs 
+Total CPU  time to Placer completion: 0 secs 
+Writing design to file TypeCheck.ncd
+
+
+
+Starting Router
+
+
+Phase  1  : 10 unrouted;      REAL time: 0 secs 
+
+Phase  2  : 10 unrouted;      REAL time: 0 secs 
+
+Phase  3  : 2 unrouted;      REAL time: 0 secs 
+
+Phase  4  : 2 unrouted; (Par is working to improve performance)     REAL time: 1 secs 
+
+Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 1 secs 
+
+Updating file: TypeCheck.ncd with current fully routed design.
+
+Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 1 secs 
+
+Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 1 secs 
+
+Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 1 secs 
+
+Total REAL time to Router completion: 1 secs 
+Total CPU time to Router completion: 1 secs 
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+Timing Score: 0 (Setup: 0, Hold: 0)
+
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+Total REAL time to PAR completion: 1 secs 
+Total CPU time to PAR completion: 1 secs 
+
+Peak Memory Usage:  600 MB
+
+Placement: Completed - No errors found.
+Routing: Completed - No errors found.
+
+Number of error messages: 0
+Number of warning messages: 0
+Number of info messages: 1
+
+Writing design to file TypeCheck.ncd
+
+
+
+PAR done!