diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index bd33367..621355e 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -99,11 +99,11 @@
     </file>
     <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -157,6 +157,16 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="OutputSelector.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="OutputSelectorTest.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="305"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="305"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="305"/>
+    </file>
   </files>
 
   <properties>
@@ -277,9 +287,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SumDataAdapter|SumDataAdapterArch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="SumDataAdapter.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SumDataAdapter" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|OutputSelector|OutputSelectorArch" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="OutputSelector.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/OutputSelector" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -348,7 +358,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="SumDataAdapter" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="OutputSelector" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -363,10 +373,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SumDataAdapter_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SumDataAdapter_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SumDataAdapter_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SumDataAdapter_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="OutputSelector_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="OutputSelector_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="OutputSelector_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="OutputSelector_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -415,8 +425,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ZeroCounterTest" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/OutputSelectorTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.OutputSelectorTest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -435,7 +445,7 @@
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.OutputSelectorTest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -491,7 +501,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ZeroCounterTest|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|OutputSelectorTest|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/OutputSelector.vhd b/OutputSelector.vhd
new file mode 100644
index 0000000..e335a05
--- /dev/null
+++ b/OutputSelector.vhd
@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity OutputSelector is
+	
+	port(
+		IS_NAN : in std_logic;
+		IS_ZERO : in std_logic;
+		IEEE_754_SUM : in std_logic_vector(31 downto 0);
+		RESULT : out std_logic_vector(31 downto 0)		
+	);
+	
+end OutputSelector;
+
+architecture OutputSelectorArch of OutputSelector is
+
+	signal NAN_OUT : std_logic_vector(31 downto 0);
+
+begin
+
+	NAN_OUT <= "0" & "11111111" & "10000000000000000000000";
+
+	SELECT_PROCESS : process (IS_NAN, IS_ZERO, IEEE_754_SUM, NAN_OUT)
+	
+	begin
+	
+		for i in 31 downto 0 loop
+			RESULT(i) <= (not(IS_NAN) and not(IS_ZERO) and IEEE_754_SUM(i)) or (IS_NAN and NAN_OUT(i));
+		end loop;
+		
+	end process;
+
+end OutputSelectorArch;
+
diff --git a/OutputSelectorTest.vhd b/OutputSelectorTest.vhd
new file mode 100644
index 0000000..4d0e1d5
--- /dev/null
+++ b/OutputSelectorTest.vhd
@@ -0,0 +1,88 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY OutputSelectorTest IS
+END OutputSelectorTest;
+ 
+ARCHITECTURE behavior OF OutputSelectorTest IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT OutputSelector
+    PORT(
+         IS_NAN : IN  std_logic;
+         IS_ZERO : IN  std_logic;
+         IEEE_754_SUM : IN  std_logic_vector(31 downto 0);
+         RESULT : OUT  std_logic_vector(31 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal IS_NAN : std_logic := '0';
+   signal IS_ZERO : std_logic := '0';
+   signal IEEE_754_SUM : std_logic_vector(31 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal RESULT : std_logic_vector(31 downto 0);
+   signal clock : std_logic; 
+ 
+   constant clock_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: OutputSelector PORT MAP (
+          IS_NAN => IS_NAN,
+          IS_ZERO => IS_ZERO,
+          IEEE_754_SUM => IEEE_754_SUM,
+          RESULT => RESULT
+        );
+
+   -- Clock process definitions
+   clock_process :process
+   begin
+		clock <= '0';
+		wait for clock_period/2;
+		clock <= '1';
+		wait for clock_period/2;
+   end process;
+ 
+
+   test_proc: process
+   begin
+		IS_NAN <= '0';
+		IS_ZERO <= '0';
+		IEEE_754_SUM <= "0" & "00111000" & "00000100100010110000110";
+      wait for clock_period;
+		IS_NAN <= '0';
+		IS_ZERO <= '0';
+		IEEE_754_SUM <= "1" & "11000010" & "00000011110010111000000";
+      wait for clock_period;
+		IS_NAN <= '0';
+		IS_ZERO <= '1';
+		IEEE_754_SUM <= "0" & "00100111" & "01111111100000000000000";
+      wait for clock_period;
+		IS_NAN <= '0';
+		IS_ZERO <= '1';
+		IEEE_754_SUM <= "1" & "00000010" & "01110000000000000000111";
+      wait for clock_period;
+		IS_NAN <= '1';
+		IS_ZERO <= '0';
+		IEEE_754_SUM <= "0" & "11111111" & "00000000000000000000000";
+      wait for clock_period;
+		IS_NAN <= '1';
+		IS_ZERO <= '0';
+		IEEE_754_SUM <= "1" & "00001111" & "10000000000000111100000";
+      wait for clock_period;
+		IS_NAN <= '1';
+		IS_ZERO <= '1';
+		IEEE_754_SUM <= "0" & "00110000" & "00000000111000000000011";
+      wait for clock_period;
+		IS_NAN <= '1';
+		IS_ZERO <= '1';
+		IEEE_754_SUM <= "1" & "11111111" & "00110011001100110011100";
+      wait for clock_period;
+	end process;
+
+END;
diff --git a/OutputSelectorTest_isim_beh.exe b/OutputSelectorTest_isim_beh.exe
new file mode 100644
index 0000000..11ae4f7
Binary files /dev/null and b/OutputSelectorTest_isim_beh.exe differ
diff --git a/OutputSelectorTest_isim_beh.wdb b/OutputSelectorTest_isim_beh.wdb
new file mode 100644
index 0000000..42eb521
Binary files /dev/null and b/OutputSelectorTest_isim_beh.wdb differ
diff --git a/PrepareForShiftTest_isim_beh.wdb b/PrepareForShiftTest_isim_beh.wdb
deleted file mode 100644
index fcf26c1..0000000
Binary files a/PrepareForShiftTest_isim_beh.wdb and /dev/null differ
diff --git a/SpecialCasesTest_isim_beh.exe b/SpecialCasesTest_isim_beh.exe
index 3209988..11ae4f7 100755
Binary files a/SpecialCasesTest_isim_beh.exe and b/SpecialCasesTest_isim_beh.exe differ
diff --git a/SumDataAdapter.vhd b/SumDataAdapter.vhd
index c77bbaa..0201fa3 100644
--- a/SumDataAdapter.vhd
+++ b/SumDataAdapter.vhd
@@ -32,19 +32,34 @@ begin
 
 	FILL <= (others => '0');
 
-	X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
+	X_FST_BIT_PROCESS : process (X_IN)
 		
-		variable X_FST_TMP : std_logic := '0';
-		variable Y_FST_TMP : std_logic := '0';
+		variable X_FST_TMP : std_logic;
 		
 	begin
 	
+		X_FST_TMP := '0';
+	
 		for i in 30 downto 23 loop
 			X_FST_TMP := X_FST_TMP or X_IN(i);
-			Y_FST_TMP := Y_FST_TMP or Y_IN(i);
 		end loop;
 		
 		X_FST_BIT <= X_FST_TMP;
+	
+	end process;
+	
+	Y_FST_BIT_PROCESS : process (Y_IN)
+		
+		variable Y_FST_TMP : std_logic;
+		
+	begin
+	
+		Y_FST_TMP := '0';
+		
+		for i in 30 downto 23 loop
+			Y_FST_TMP := Y_FST_TMP or Y_IN(i);
+		end loop;
+		
 		Y_FST_BIT <= Y_FST_TMP;
 	
 	end process;
@@ -54,7 +69,7 @@ begin
 	SHIFTER : ShiftRight48
 		port map (N => N, PLACES => DIFF_EXP, RESULT => Y_OUT);
 
-	--X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL;
+		X_OUT <= X_FST_BIT & X_IN(22 downto 0) & FILL;
 	
 end SumDataAdapterArch;
 
diff --git a/SumDataAdapterTest.vhd b/SumDataAdapterTest.vhd
index 3ee3dc4..746539f 100644
--- a/SumDataAdapterTest.vhd
+++ b/SumDataAdapterTest.vhd
@@ -67,36 +67,36 @@ BEGIN
 	
 	test_process :process
    begin
-		X_IN <= "111111110000010001000100000000";
-		Y_IN <= "001001000000000010001000000000";
+		X_IN <= "1111111100000100010001000000000";
+		Y_IN <= "0010010000000000100010000000000";
 		DIFF_EXP <= "000000000"; --0
 		wait for clock_period;
-		X_IN <= "000000000000100000000001000000";
-		Y_IN <= "000000000000001111111000000000";
+		X_IN <= "0000000000001000000000010000000";
+		Y_IN <= "0000000000000011111110000000000";
 		DIFF_EXP <= "000001000"; --8
 		wait for clock_period;
-		X_IN <= "000000000000000000111000000000";
-		Y_IN <= "000010000000000000000000000111";
+		X_IN <= "0000000000000000001110000000000";
+		Y_IN <= "0000100000000000000000000001111";
 		DIFF_EXP <= "010011100"; --156
 		wait for clock_period;
-		X_IN <= "000000100000000000000000000000";
-		Y_IN <= "000000001000000001111111111111";
+		X_IN <= "0000001000000000000000000000000";
+		Y_IN <= "0000000010000000011111111111111";
 		DIFF_EXP <= "000110000"; --48
 		wait for clock_period;
-		X_IN <= "000000000000000000000000010000";
-		Y_IN <= "000000000000000000011100000000";
+		X_IN <= "0000000000000000000000000100000";
+		Y_IN <= "0000000000000000000111000000000";
 		DIFF_EXP <= "111111111"; --511
 		wait for clock_period;
-		X_IN <= "000000000000000000000000000000";
-		Y_IN <= "000000000000011100000000000000";
+		X_IN <= "0000000000000000000000000000000";
+		Y_IN <= "0000000000000111000000000000000";
 		DIFF_EXP <= "000100100"; --36
 		wait for clock_period;
-		X_IN <= "000000000000000000000000000000";
-		Y_IN <= "000000000000000000000000000000";
+		X_IN <= "0000000000000000000000000000000";
+		Y_IN <= "0000000000000000000000000000000";
 		DIFF_EXP <= "000001101"; --13
 		wait for clock_period;
-		X_IN <= "000000000000000001110001100100";
-		Y_IN <= "000000000000000000000011110000";
+		X_IN <= "0000000000000000011100011001000";
+		Y_IN <= "0000000000000000000000111100000";
 		DIFF_EXP <= "000011111"; --31
 		wait for clock_period;
    end process;
diff --git a/SumDataAdapterTest_isim_beh.exe b/SumDataAdapterTest_isim_beh.exe
new file mode 100644
index 0000000..11ae4f7
Binary files /dev/null and b/SumDataAdapterTest_isim_beh.exe differ
diff --git a/fuse.log b/fuse.log
index df18e94..6e4d842 100644
--- a/fuse.log
+++ b/fuse.log
@@ -1,23 +1,21 @@
-Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj work.ZeroCounterTest 
-ISim P.20131013 (signature 0xfbc00daa)
-Number of CPUs detected in this system: 4
-Turning on mult-threading, number of parallel sub-compilation jobs: 8 
+Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/OutputSelectorTest_beh.prj work.OutputSelectorTest 
+ISim P.20160913 (signature 0xfbc00daa)
+Number of CPUs detected in this system: 1
+Turning on mult-threading, number of parallel sub-compilation jobs: 0 
 Determining compilation order of HDL files
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelector.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelectorTest.vhd" into library work
 Starting static elaboration
 Completed static elaboration
-Fuse Memory Usage: 95772 KB
-Fuse CPU Usage: 1030 ms
+Fuse Memory Usage: 95300 KB
+Fuse CPU Usage: 2310 ms
 Compiling package standard
 Compiling package std_logic_1164
-Compiling package numeric_std
-Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(8,3)\]
-Compiling architecture behavior of entity zerocountertest
+Compiling architecture outputselectorarch of entity OutputSelector [outputselector_default]
+Compiling architecture behavior of entity outputselectortest
 Time Resolution for simulation is 1ps.
-Waiting for 1 sub-compilation(s) to finish...
-Compiled 6 VHDL Units
-Built simulation executable /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe
-Fuse Memory Usage: 665500 KB
-Fuse CPU Usage: 1100 ms
-GCC CPU Usage: 170 ms
+Compiled 5 VHDL Units
+Built simulation executable /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe
+Fuse Memory Usage: 103948 KB
+Fuse CPU Usage: 2410 ms
+GCC CPU Usage: 550 ms
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
index ec10f88..27fca25 100644
--- a/fuseRelaunch.cmd
+++ b/fuseRelaunch.cmd
@@ -1 +1 @@
--intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj" "work.ZeroCounterTest" 
+-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/OutputSelectorTest_beh.prj" "work.OutputSelectorTest"