lucacuzzocrea/IEEE754Adder
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Aggiunti ShiftLeft e ZeroCounter

Browse Source
This commit is contained in:
Luca Cuzzocrea
2019-09-08 15:20:19 +02:00
parent 0250f39c47
commit 5a2605e685
11 changed files with 331 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
IEEE754Adder.xise
View File

@@ -98,11 +98,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
@@ -110,7 +110,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="266"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="266"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="266"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="266"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="266"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="266"/>
@@ -139,6 +139,24 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="279"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="279"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
</file> </file>
<file xil_pn:name="ZeroCounter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ZeroCounterTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="255"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="255"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="255"/>
</file>
<file xil_pn:name="ShiftLeft.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="UTILS.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files> </files>
<properties> <properties>
@@ -397,8 +415,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SumDataAdapterTest" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ZeroCounterTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -417,7 +435,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SumDataAdapterTest" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -473,7 +491,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SumDataAdapterTest|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|ZeroCounterTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

80
ShiftLeft.vhd Normal file
View File

@@ -0,0 +1,80 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.UTILS.ALL;
entity ShiftLeft48 is
port(
N : in std_logic_vector(47 downto 0);
PLACES : in std_logic_vector(8 downto 0);
RESULT : out std_logic_vector(47 downto 0)
);
end ShiftLeft48;
architecture ShiftLeftArch of ShiftLeft48 is
begin
shift_process: process (N, PLACES)
variable POSSIBLE_SHIFTS : ARRAY_OF_STD_LOGIC48;
begin
case PLACES is
when "000000000" => RESULT <= N( 47 downto 0 );
when "000000001" => RESULT <= N( 46 downto 0 ) & "0";
when "000000010" => RESULT <= N( 45 downto 0 ) & "00";
when "000000011" => RESULT <= N( 44 downto 0 ) & "000";
when "000000100" => RESULT <= N( 43 downto 0 ) & "0000";
when "000000101" => RESULT <= N( 42 downto 0 ) & "00000";
when "000000110" => RESULT <= N( 41 downto 0 ) & "000000";
when "000000111" => RESULT <= N( 40 downto 0 ) & "0000000";
when "000001000" => RESULT <= N( 39 downto 0 ) & "00000000";
when "000001001" => RESULT <= N( 38 downto 0 ) & "000000000";
when "000001010" => RESULT <= N( 37 downto 0 ) & "0000000000";
when "000001011" => RESULT <= N( 36 downto 0 ) & "00000000000";
when "000001100" => RESULT <= N( 35 downto 0 ) & "000000000000";
when "000001101" => RESULT <= N( 34 downto 0 ) & "0000000000000";
when "000001110" => RESULT <= N( 33 downto 0 ) & "00000000000000";
when "000001111" => RESULT <= N( 32 downto 0 ) & "000000000000000";
when "000010000" => RESULT <= N( 31 downto 0 ) & "0000000000000000";
when "000010001" => RESULT <= N( 30 downto 0 ) & "00000000000000000";
when "000010010" => RESULT <= N( 29 downto 0 ) & "000000000000000000";
when "000010011" => RESULT <= N( 28 downto 0 ) & "0000000000000000000";
when "000010100" => RESULT <= N( 27 downto 0 ) & "00000000000000000000";
when "000010101" => RESULT <= N( 26 downto 0 ) & "000000000000000000000";
when "000010110" => RESULT <= N( 25 downto 0 ) & "0000000000000000000000";
when "000010111" => RESULT <= N( 24 downto 0 ) & "00000000000000000000000";
when "000011000" => RESULT <= N( 23 downto 0 ) & "000000000000000000000000";
when "000011001" => RESULT <= N( 22 downto 0 ) & "0000000000000000000000000";
when "000011010" => RESULT <= N( 21 downto 0 ) & "00000000000000000000000000";
when "000011011" => RESULT <= N( 20 downto 0 ) & "000000000000000000000000000";
when "000011100" => RESULT <= N( 19 downto 0 ) & "0000000000000000000000000000";
when "000011101" => RESULT <= N( 18 downto 0 ) & "00000000000000000000000000000";
when "000011110" => RESULT <= N( 17 downto 0 ) & "000000000000000000000000000000";
when "000011111" => RESULT <= N( 16 downto 0 ) & "0000000000000000000000000000000";
when "000100000" => RESULT <= N( 15 downto 0 ) & "00000000000000000000000000000000";
when "000100001" => RESULT <= N( 14 downto 0 ) & "000000000000000000000000000000000";
when "000100010" => RESULT <= N( 13 downto 0 ) & "0000000000000000000000000000000000";
when "000100011" => RESULT <= N( 12 downto 0 ) & "00000000000000000000000000000000000";
when "000100100" => RESULT <= N( 11 downto 0 ) & "000000000000000000000000000000000000";
when "000100101" => RESULT <= N( 10 downto 0 ) & "0000000000000000000000000000000000000";
when "000100110" => RESULT <= N( 9 downto 0 ) & "00000000000000000000000000000000000000";
when "000100111" => RESULT <= N( 8 downto 0 ) & "000000000000000000000000000000000000000";
when "000101000" => RESULT <= N( 7 downto 0 ) & "0000000000000000000000000000000000000000";
when "000101001" => RESULT <= N( 6 downto 0 ) & "00000000000000000000000000000000000000000";
when "000101010" => RESULT <= N( 5 downto 0 ) & "000000000000000000000000000000000000000000";
when "000101011" => RESULT <= N( 4 downto 0 ) & "0000000000000000000000000000000000000000000";
when "000101100" => RESULT <= N( 3 downto 0 ) & "00000000000000000000000000000000000000000000";
when "000101101" => RESULT <= N( 2 downto 0 ) & "000000000000000000000000000000000000000000000";
when "000101110" => RESULT <= N( 1 downto 0 ) & "0000000000000000000000000000000000000000000000";
when "000101111" => RESULT <= N( 0 ) & "00000000000000000000000000000000000000000000000";
when others => RESULT <= "000000000000000000000000000000000000000000000000";
end case;
end process;
end ShiftLeftArch;

63
UTILS.vhd Normal file
View File

@@ -0,0 +1,63 @@
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package UTILS is
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
type ARRAY_OF_STD_LOGIC48 is array (0 to 512) of std_logic_vector(47 downto 0);
end UTILS;
package body UTILS is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end UTILS;

60
ZeroCounter.vhd Normal file
View File

@@ -0,0 +1,60 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ZeroCounter is
generic(
BITCOUNT : integer := 8;
RES_BITCOUNT : integer := 3 -- MUST BE >= CEIL( LOG2( BITCOUNT ) )
);
port(
X : in std_logic_vector( (BITCOUNT-1) downto 0 );
Z_COUNT : out std_logic_vector( (RES_BITCOUNT-1) downto 0 );
ALL_ZEROS : out std_logic
);
end ZeroCounter;
architecture ZeroCounterArch of ZeroCounter is
begin
ZEROCOUNT_PROCESS: process (X)
variable ZC: std_logic_vector((RES_BITCOUNT-1) downto 0);
variable BIN_N: std_logic_vector((RES_BITCOUNT-1) downto 0);
variable PART_ZC: std_logic_vector((BITCOUNT-1) downto 0);
begin
ZC := ((RES_BITCOUNT-1) downto 0 => '0');
PART_ZC := ((BITCOUNT-1) downto 0 => '1');
for N in 1 to (BITCOUNT-1) loop
-- compute partial logic to add to result's '1' bits
for p_i in (BITCOUNT-1) downto (BITCOUNT-N) loop
PART_ZC(N) := PART_ZC(N) and (not X(p_i));
end loop;
PART_ZC(N) := PART_ZC(N) and X(BITCOUNT-1-N);
-- add partial logic to result
BIN_N := std_logic_vector(to_unsigned(N, BIN_N'length));
for res_i in (RES_BITCOUNT-1) downto 0 loop
if ( BIN_N(res_i) = '1' ) then
ZC(res_i) := ZC(res_i) or PART_ZC(N);
end if;
end loop;
end loop;
Z_COUNT <= ZC;
end process;
ALLZERO_PROCESS: process (X)
variable AZ : std_logic;
begin
AZ := '1';
for i in X'range loop
AZ := AZ and (not X(i));
end loop;
ALL_ZEROS <= AZ;
end process;
end ZeroCounterArch;

79
ZeroCounterTest.vhd Normal file
View File

@@ -0,0 +1,79 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ZeroCounterTest IS
END ZeroCounterTest;
ARCHITECTURE behavior OF ZeroCounterTest IS
COMPONENT ZeroCounter
PORT(
X : IN std_logic_vector(7 downto 0);
Z_COUNT : OUT std_logic_vector(2 downto 0);
ALL_ZEROS : OUT std_logic
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal Z_COUNT : std_logic_vector(2 downto 0);
signal ALL_ZEROS : std_logic;
constant clock_period : time := 10 ns;
signal clock: std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ZeroCounter PORT MAP (
X => X,
Z_COUNT => Z_COUNT,
ALL_ZEROS => ALL_ZEROS
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
stim_proc: process
begin
X <= "00000000";
wait for clock_period;
X <= "00000001";
wait for clock_period;
X <= "00000010";
wait for clock_period;
X <= "00000100";
wait for clock_period;
X <= "00001000";
wait for clock_period;
X <= "00010000";
wait for clock_period;
X <= "00100000";
wait for clock_period;
X <= "01000000";
wait for clock_period;
X <= "10000000";
wait for clock_period;
X <= "00100110";
wait for clock_period;
X <= "11111111";
wait for clock_period;
X <= "01111111";
wait for clock_period;
X <= "00111111";
wait for clock_period;
X <= "00101111";
wait for clock_period;
end process;
END;

BIN
ZeroCounterTest_isim_beh.exe Executable file
View File

Binary file not shown.

BIN
ZeroCounterTest_isim_beh.wdb Normal file
View File

Binary file not shown.

30
fuse.log
View File

@@ -1,11 +1,23 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj work.ZeroCounterTest
ISim P.20160913 (signature 0xfbc00daa) ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1 Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 0 Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
Starting static elaboration Starting static elaboration
ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31 Completed static elaboration
ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed Fuse Memory Usage: 95772 KB
Fuse CPU Usage: 1030 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(8,3)\]
Compiling architecture behavior of entity zerocountertest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe
Fuse Memory Usage: 665500 KB
Fuse CPU Usage: 1100 ms
GCC CPU Usage: 170 ms

6
fuse.xmsgs
View File

@@ -5,11 +5,5 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="error" file="HDLCompiler" num="410" delta="unknown" >"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has <arg fmt="%d" index="1">30</arg> elements ; expected <arg fmt="%d" index="2">31</arg>
</msg>
<msg type="error" file="Simulator" num="777" delta="unknown" >Static elaboration of top level VHDL design unit <arg fmt="%s" index="1">sumdataadaptertest</arg> in library <arg fmt="%s" index="2">work</arg> failed
</msg>
</messages> </messages>

2
fuseRelaunch.cmd
View File

@@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj" "work.SumDataAdapterTest" -intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/ZeroCounterTest_beh.prj" "work.ZeroCounterTest"