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Aggiunto controllo risultato NaN

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This commit is contained in:
Luca Cuzzocrea
2019-08-17 18:45:31 +02:00
parent a1b9650580
commit 47cc74e0d0
18 changed files with 380 additions and 109 deletions
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203
SpecialCasesCheck.syr
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@@ -5,14 +5,14 @@ Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
Total CPU time to Xst completion: 0.05 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
Total CPU time to Xst completion: 0.05 secs
-->
Reading design: SpecialCasesCheck.prj
@@ -107,20 +107,199 @@ Slice Utilization Ratio Delta : 5
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work.
Architecture typecheckarch of Entity typecheck is up to date.
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
Entity <typecheck> compiled.
Entity <typecheck> (Architecture <typecheckarch>) compiled.
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist.
Entity <specialcasescheck> compiled.
Entity <specialcasescheck> (Architecture <specialcasescheckarch>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <SpecialCasesCheck> in library <work> (architecture <specialcasescheckarch>).
Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <SpecialCasesCheck> in library <work> (Architecture <specialcasescheckarch>).
Entity <SpecialCasesCheck> analyzed. Unit <SpecialCasesCheck> generated.
Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <TypeCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <TypeCheck> synthesized.
Synthesizing Unit <SpecialCasesCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
Unit <SpecialCasesCheck> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <SpecialCasesCheck> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : SpecialCasesCheck.ngr
Top Level Output File Name : SpecialCasesCheck
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 66
Cell Usage :
# BELS : 24
# GND : 1
# LUT2 : 1
# LUT3 : 2
# LUT4 : 20
# IO Buffers : 66
# IBUF : 64
# OBUF : 2
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-5
Number of Slices: 13 out of 768 1%
Number of 4 input LUTs: 23 out of 1536 1%
Number of IOs: 66
Number of bonded IOBs: 66 out of 124 53%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 13.307ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 72 / 1
-------------------------------------------------------------------------
Delay: 13.307ns (Levels of Logic = 7)
Source: Y<8> (PAD)
Destination: isNan (PAD)
Data Path: Y<8> to isNan
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF)
LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35)
LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41)
LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61)
LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6)
LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF)
OBUF:I->O 4.909 isNan_OBUF (isNan)
----------------------------------------
Total 13.307ns (8.019ns logic, 5.288ns route)
(60.3% logic, 39.7% route)
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.05 secs
-->
Total memory usage is 584420 kilobytes
Total memory usage is 606300 kilobytes
Number of errors : 5 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)