From 3bc4d7a489a0bdf5667b4eb0ddfdfa89b3f1dc89 Mon Sep 17 00:00:00 2001
From: Luca Cuzzocrea <luca@cuzzocrea.xyz>
Date: Sun, 8 Sep 2019 23:26:50 +0200
Subject: [PATCH] Inizio test sommatore finale

---
 IEEE754Adder.xise             |  66 ++++++++++----------
 IEEE754AdderTest.vhd          | 109 ++++++++++++++++++++++++++++++++++
 IEEE754AdderTest_isim_beh.exe | Bin 0 -> 21792 bytes
 fuse.log                      |  70 ++++++++++++++++++----
 fuseRelaunch.cmd              |   2 +-
 5 files changed, 203 insertions(+), 44 deletions(-)
 create mode 100644 IEEE754AdderTest.vhd
 create mode 100755 IEEE754AdderTest_isim_beh.exe

diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index f45da8d..d404ff1 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -16,23 +16,23 @@
 
   <files>
     <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
@@ -42,7 +42,7 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
     </file>
     <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
@@ -52,11 +52,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
     <file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
@@ -66,11 +66,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
     </file>
     <file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
@@ -80,11 +80,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
     </file>
     <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
@@ -94,19 +94,19 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="179"/>
     </file>
     <file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
@@ -140,7 +140,7 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
     </file>
     <file xil_pn:name="ZeroCounter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ZeroCounterTest.vhd" xil_pn:type="FILE_VHDL">
@@ -150,7 +150,7 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="255"/>
     </file>
     <file xil_pn:name="ShiftLeft.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="UTILS.vhd" xil_pn:type="FILE_VHDL">
@@ -158,7 +158,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="OutputSelector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="OutputSelectorTest.vhd" xil_pn:type="FILE_VHDL">
@@ -168,35 +168,41 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="305"/>
     </file>
     <file xil_pn:name="PipelineStageOne.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="PipelineStageTwo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="PipelineStageThree.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="IEEE754Adder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="FlipFlopD.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="FlipFlopDVector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="NormalizerTest.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="336"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="336"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="336"/>
     </file>
+    <file xil_pn:name="IEEE754AdderTest.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="341"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="341"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="341"/>
+    </file>
   </files>
 
   <properties>
@@ -455,8 +461,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/NormalizerTest" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.NormalizerTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IEEE754AdderTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IEEE754AdderTest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -475,7 +481,7 @@
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.NormalizerTest" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IEEE754AdderTest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -531,7 +537,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|NormalizerTest|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|IEEE754AdderTest|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/IEEE754AdderTest.vhd b/IEEE754AdderTest.vhd
new file mode 100644
index 0000000..cc0d8a2
--- /dev/null
+++ b/IEEE754AdderTest.vhd
@@ -0,0 +1,109 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ 
+ENTITY IEEE754AdderTest IS
+END IEEE754AdderTest;
+ 
+ARCHITECTURE behavior OF IEEE754AdderTest IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT IEEE754Adder
+    PORT(
+         X : IN  std_logic_vector(31 downto 0);
+         Y : IN  std_logic_vector(31 downto 0);
+         RESET : IN  std_logic;
+         CLK : IN  std_logic;
+         RESULT : OUT  std_logic_vector(31 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal X : std_logic_vector(31 downto 0) := (others => '0');
+   signal Y : std_logic_vector(31 downto 0) := (others => '0');
+   signal RESET : std_logic := '0';
+   signal CLK : std_logic := '0';
+
+ 	--Outputs
+   signal RESULT : std_logic_vector(31 downto 0);
+
+   -- Clock period definitions
+   constant CLK_period : time := 100 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: IEEE754Adder PORT MAP (
+          X => X,
+          Y => Y,
+          RESET => RESET,
+          CLK => CLK,
+          RESULT => RESULT
+        );
+
+   -- Clock process definitions
+   CLK_process :process
+   begin
+		CLK <= '0';
+		wait for CLK_period/2;
+		CLK <= '1';
+		wait for CLK_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      RESET <= '1';
+      wait for 400 ns;
+		RESET <= '0';
+
+		-- TODO: FINIRE TEST
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00001000000000000000111000000000";
+		Y <= "00000010000001111000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000000000000000000000000000";
+		Y <= "00000000000000000000000000000000";
+      wait;
+   end process;
+
+END;
diff --git a/IEEE754AdderTest_isim_beh.exe b/IEEE754AdderTest_isim_beh.exe
new file mode 100755
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diff --git a/fuse.log b/fuse.log
index eeb1191..483896c 100644
--- a/fuse.log
+++ b/fuse.log
@@ -1,36 +1,80 @@
-Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/NormalizerTest_beh.prj work.NormalizerTest 
+Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_beh.prj work.IEEE754AdderTest 
 ISim P.20131013 (signature 0xfbc00daa)
 Number of CPUs detected in this system: 4
 Turning on mult-threading, number of parallel sub-compilation jobs: 8 
 Determining compilation order of HDL files
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/UTILS.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ShiftRight.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ShiftLeft.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Comparator.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TwoComplement.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Swap.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SumDataAdapter.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/PrepareForShift.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/OutputSelector.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/OperationCheck.vhd" into library work
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Normalizer.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NormalizerTest.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/CarryLookAhead.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/PipelineStageTwo.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/PipelineStageThree.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/PipelineStageOne.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/FlipFlopDVector.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/FlipFlopD.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754Adder.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754AdderTest.vhd" into library work
 Starting static elaboration
 Completed static elaboration
-Fuse Memory Usage: 96516 KB
-Fuse CPU Usage: 1020 ms
+Fuse Memory Usage: 97552 KB
+Fuse CPU Usage: 990 ms
 Compiling package standard
 Compiling package std_logic_1164
+Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(32)\]
+Compiling architecture typecheckarch of entity TypeCheck [typecheck_default]
+Compiling architecture nancheckarch of entity NaNCheck [nancheck_default]
+Compiling architecture equalcheckarch of entity EqualCheck [\EqualCheck(31)\]
+Compiling architecture zerocheckarch of entity ZeroCheck [zerocheck_default]
+Compiling architecture specialcasescheckarch of entity SpecialCasesCheck [specialcasescheck_default]
+Compiling architecture comparatorarch of entity Comparator [\Comparator(23)\]
+Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
+Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
+Compiling architecture prepareforshiftarch of entity PrepareForShift [prepareforshift_default]
+Compiling architecture swaparch of entity Swap [\Swap(32)\]
+Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(9)\]
+Compiling architecture stageonearch of entity PipelineStageOne [pipelinestageone_default]
+Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(9)\]
+Compiling architecture flipflopdarch of entity FlipFlopD [flipflopd_default]
+Compiling architecture shiftrightarch of entity ShiftRight48 [shiftright48_default]
+Compiling architecture sumdataadapterarch of entity SumDataAdapter [sumdataadapter_default]
+Compiling architecture operationcheckarch of entity OperationCheck [operationcheck_default]
+Compiling architecture carrylookaheadarch of entity Adder [\Adder(48)\]
+Compiling architecture addsubarch of entity AddSub [\AddSub(48)\]
+Compiling architecture carrylookaheadarch of entity CarryLookAhead [carrylookahead_default]
+Compiling architecture stagetwoarch of entity PipelineStageTwo [pipelinestagetwo_default]
+Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(8)\]
+Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(48)\]
 Compiling package numeric_std
 Compiling package math_real
 Compiling package utils
 Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(48,8)\]
 Compiling architecture comparatorarch of entity Comparator [\Comparator(8)\]
-Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
-Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
 Compiling architecture shiftleftarch of entity ShiftLeft48 [shiftleft48_default]
 Compiling architecture normalizerarch of entity Normalizer [normalizer_default]
-Compiling architecture behavior of entity normalizertest
+Compiling architecture outputselectorarch of entity OutputSelector [outputselector_default]
+Compiling architecture stagethreearch of entity PipelineStageThree [pipelinestagethree_default]
+Compiling architecture behavioral of entity IEEE754Adder [ieee754adder_default]
+Compiling architecture behavior of entity ieee754addertest
 Time Resolution for simulation is 1ps.
-Waiting for 1 sub-compilation(s) to finish...
-Compiled 18 VHDL Units
-Built simulation executable /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe
-Fuse Memory Usage: 670604 KB
-Fuse CPU Usage: 1130 ms
-GCC CPU Usage: 480 ms
+Waiting for 2 sub-compilation(s) to finish...
+Compiled 68 VHDL Units
+Built simulation executable /home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_isim_beh.exe
+Fuse Memory Usage: 671904 KB
+Fuse CPU Usage: 1160 ms
+GCC CPU Usage: 1140 ms
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
index 4f1cf30..90d54e9 100644
--- a/fuseRelaunch.cmd
+++ b/fuseRelaunch.cmd
@@ -1 +1 @@
--intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/NormalizerTest_beh.prj" "work.NormalizerTest" 
+-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_beh.prj" "work.IEEE754AdderTest"