Aggiunto modulo OutputSelector con test

This commit is contained in:
2019-09-07 15:54:31 +02:00
parent 0250f39c47
commit 3b54fbe6a0
13 changed files with 202 additions and 51 deletions

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@@ -5,11 +5,5 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="410" delta="unknown" >"/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has <arg fmt="%d" index="1">30</arg> elements ; expected <arg fmt="%d" index="2">31</arg>
</msg>
<msg type="error" file="Simulator" num="777" delta="unknown" >Static elaboration of top level VHDL design unit <arg fmt="%s" index="1">sumdataadaptertest</arg> in library <arg fmt="%s" index="2">work</arg> failed
</msg>
</messages>