From 2ecaee1b198cb9994944cded52474e8ebd1a2a1a Mon Sep 17 00:00:00 2001 From: Giulio Date: Sat, 17 Aug 2019 19:22:19 +0200 Subject: [PATCH] Refactoring controllo NaN --- IEEE754Adder.gise | 41 +-- IEEE754Adder.xise | 132 ++++---- NaNCheck.vhd | 38 +++ SpecialCasesCheck.cmd_log | 3 + SpecialCasesCheck.ngc | 2 +- SpecialCasesCheck.ngr | 2 +- SpecialCasesCheck.prj | 1 + SpecialCasesCheck.syr | 205 +++++------ SpecialCasesCheck.vhd | 19 +- SpecialCasesCheck.xst | 22 +- SpecialCasesCheck_envsettings.html | 123 ++++--- SpecialCasesCheck_summary.html | 36 +- SpecialCasesCheck_xst.xrpt | 157 ++++----- TypeCheck_envsettings.html | 509 ++++++++++++++++++++++++++++ TypeCheck_summary.html | 102 ++++++ _xmsgs/pn_parser.xmsgs | 2 +- _xmsgs/xst.xmsgs | 2 +- iseconfig/IEEE754Adder.projectmgr | 76 +++++ iseconfig/SpecialCasesCheck.xreport | 6 +- iseconfig/TypeCheck.xreport | 215 ++++++++++++ webtalk_pn.xml | 36 +- xst/work/work.vdbl | Bin 0 -> 12608 bytes xst/work/work.vdbx | Bin 0 -> 128 bytes 23 files changed, 1337 insertions(+), 392 deletions(-) create mode 100644 NaNCheck.vhd create mode 100644 TypeCheck_envsettings.html create mode 100644 TypeCheck_summary.html create mode 100644 iseconfig/IEEE754Adder.projectmgr create mode 100644 iseconfig/TypeCheck.xreport create mode 100644 xst/work/work.vdbl create mode 100644 xst/work/work.vdbx diff --git a/IEEE754Adder.gise b/IEEE754Adder.gise index dce5a88..5a05a93 100644 --- a/IEEE754Adder.gise +++ b/IEEE754Adder.gise @@ -85,6 +85,7 @@ + @@ -110,8 +111,9 @@ - + + @@ -120,23 +122,22 @@ + - + - - + - @@ -145,39 +146,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise index e2972ab..c37b586 100644 --- a/IEEE754Adder.xise +++ b/IEEE754Adder.xise @@ -17,17 +17,21 @@ - + + + + + - - + + @@ -41,8 +45,6 @@ - - @@ -50,8 +52,8 @@ - - + + @@ -61,64 +63,65 @@ - - - + + - + - - - - - + + + - + - + - + - + + - + - - + + + + + - - + - + + @@ -137,12 +140,10 @@ - + - - @@ -160,7 +161,6 @@ - @@ -173,29 +173,35 @@ - + - - + + + + + + + - + - + + @@ -216,13 +222,13 @@ - + - + @@ -231,9 +237,8 @@ - - + @@ -249,10 +254,9 @@ - - + @@ -266,10 +270,10 @@ - + @@ -278,7 +282,6 @@ - @@ -286,9 +289,10 @@ - + + - + @@ -303,14 +307,13 @@ - - - + + - + @@ -318,7 +321,7 @@ - + @@ -331,28 +334,25 @@ - + - - - + + - + - - + - - - - + + + @@ -360,17 +360,17 @@ - + - - - - + + + + diff --git a/NaNCheck.vhd b/NaNCheck.vhd new file mode 100644 index 0000000..1ba7ed4 --- /dev/null +++ b/NaNCheck.vhd @@ -0,0 +1,38 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity NaNCheck is + port( + X, Y: in std_logic_vector(31 downto 0); + isNan: out std_logic + ); +end NaNCheck; + +architecture NaNCheckArch of NaNCheck is + component TypeCheck is + port( + N: in std_logic_vector(31 downto 0); + NaN, INF: out std_logic + ); + end component; + + signal xNan: std_logic; + signal xInf: std_logic; + signal xSign: std_logic; + signal yNan: std_logic; + signal yInf: std_logic; + signal ySign: std_logic; + +begin + xCheck: TypeCheck + port map (N => X, NaN => xNan, INF => xInf); + yCheck: TypeCheck + port map (N => Y, NaN => yNan, INF => yInf); + + xSign <= X(31); + ySign <= Y(31); + + isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign); + +end NaNCheckArch; + diff --git a/SpecialCasesCheck.cmd_log b/SpecialCasesCheck.cmd_log index 1168b5f..727d9bb 100644 --- a/SpecialCasesCheck.cmd_log +++ b/SpecialCasesCheck.cmd_log @@ -5,3 +5,6 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" diff --git a/SpecialCasesCheck.ngc b/SpecialCasesCheck.ngc index 129b4db..35a11a9 100644 --- a/SpecialCasesCheck.ngc +++ b/SpecialCasesCheck.ngc @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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\ No newline at end of file diff --git a/SpecialCasesCheck.ngr b/SpecialCasesCheck.ngr index 8e3b39e..c97eb0e 100644 --- a/SpecialCasesCheck.ngr +++ b/SpecialCasesCheck.ngr @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6e 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+1,42 @@ -Release 14.7 - xst P.20131013 (lin64) +Release 14.7 - xst P.20160913 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.05 secs +Total CPU time to Xst completion: 0.09 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.05 secs +Total CPU time to Xst completion: 0.09 secs --> Reading design: SpecialCasesCheck.prj TABLE OF CONTENTS 1) Synthesis Options Summary - 2) HDL Compilation - 3) Design Hierarchy Analysis - 4) HDL Analysis - 5) HDL Synthesis - 5.1) HDL Synthesis Report - 6) Advanced HDL Synthesis - 6.1) Advanced HDL Synthesis Report - 7) Low Level Synthesis - 8) Partition Report - 9) Final Report - 9.1) Device utilization summary - 9.2) Partition Resource Summary - 9.3) TIMING REPORT + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report ========================================================================= @@ -39,13 +44,12 @@ TABLE OF CONTENTS ========================================================================= ---- Source Parameters Input File Name : "SpecialCasesCheck.prj" -Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "SpecialCasesCheck" Output Format : NGC -Target Device : xc3s50-5-pq208 +Target Device : xa6slx4-3-csg225 ---- Source Options Top Module Name : SpecialCasesCheck @@ -56,25 +60,21 @@ FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes -Mux Style : Auto -Decoder Extraction : YES -Priority Encoder Extraction : Yes Shift Register Extraction : YES -Logical Shifter Extraction : YES -XOR Collapsing : YES ROM Style : Auto -Mux Extraction : Yes Resource Sharing : YES Asynchronous To Synchronous : NO -Multiplier Style : Auto +Shift Register Minimum Size : 2 +Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto Add IO Buffers : YES -Global Maximum Fanout : 500 -Add Generic Clock Buffer(BUFG) : 8 +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 32 Register Duplication : YES -Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes @@ -85,6 +85,7 @@ Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 +Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes @@ -97,7 +98,7 @@ Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 -Verilog 2001 : YES +DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 @@ -105,48 +106,50 @@ Slice Utilization Ratio Delta : 5 ========================================================================= -* HDL Compilation * +* HDL Parsing * ========================================================================= -Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work. -Architecture typecheckarch of Entity typecheck is up to date. -Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work. -Entity compiled. -Entity (Architecture ) compiled. +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work +Parsing entity . +Parsing architecture of entity . ========================================================================= -* Design Hierarchy Analysis * +* HDL Elaboration * ========================================================================= -Analyzing hierarchy for entity in library (architecture ). -Analyzing hierarchy for entity in library (architecture ). +Elaborating entity (architecture ) from library . +Elaborating entity (architecture ) from library . -========================================================================= -* HDL Analysis * -========================================================================= -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - -Analyzing Entity in library (Architecture ). -Entity analyzed. Unit generated. - +Elaborating entity (architecture ) from library . ========================================================================= * HDL Synthesis * ========================================================================= -Performing bidirectional port resolution... - -Synthesizing Unit . - Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd". -WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. -Unit synthesized. - - Synthesizing Unit . - Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd". + Related source file is "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd". + Summary: + no macro. Unit synthesized. +Synthesizing Unit . + Related source file is "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Summary: + no macro. +Unit synthesized. ========================================================================= HDL Synthesis Report @@ -173,7 +176,7 @@ Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1. +Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 0. Final Macro Processing ... @@ -195,38 +198,45 @@ Partition Implementation Status ------------------------------- ========================================================================= -* Final Report * +* Design Summary * ========================================================================= -Final Results -RTL Top Level Output File Name : SpecialCasesCheck.ngr -Top Level Output File Name : SpecialCasesCheck -Output Format : NGC -Optimization Goal : Speed -Keep Hierarchy : No -Design Statistics -# IOs : 66 +Top Level Output File Name : SpecialCasesCheck.ngc -Cell Usage : -# BELS : 24 +Primitive and Black Box Usage: +------------------------------ +# BELS : 16 # GND : 1 -# LUT2 : 1 # LUT3 : 2 -# LUT4 : 20 +# LUT4 : 2 +# LUT5 : 2 +# LUT6 : 9 # IO Buffers : 66 # IBUF : 64 # OBUF : 2 -========================================================================= Device utilization summary: --------------------------- -Selected Device : 3s50pq208-5 +Selected Device : xa6slx4csg225-3 - Number of Slices: 13 out of 768 1% - Number of 4 input LUTs: 23 out of 1536 1% + +Slice Logic Utilization: + Number of Slice LUTs: 15 out of 2400 0% + Number used as Logic: 15 out of 2400 0% + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 15 + Number with an unused Flip Flop: 15 out of 15 100% + Number with an unused LUT: 0 out of 15 0% + Number of fully used LUT-FF pairs: 0 out of 15 0% + Number of unique control sets: 0 + +IO Utilization: Number of IOs: 66 - Number of bonded IOBs: 66 out of 124 53% + Number of bonded IOBs: 66 out of 132 50% + +Specific Feature Utilization: --------------------------- Partition Resource Summary: @@ -238,7 +248,7 @@ Partition Resource Summary: ========================================================================= -TIMING REPORT +Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT @@ -254,50 +264,53 @@ No asynchronous control signals found in this design Timing Summary: --------------- -Speed Grade: -5 +Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found - Maximum combinational path delay: 13.307ns + Maximum combinational path delay: 7.532ns -Timing Detail: --------------- +Timing Details: +--------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 72 / 1 + Total number of paths / destination ports: 64 / 1 ------------------------------------------------------------------------- -Delay: 13.307ns (Levels of Logic = 7) - Source: Y<8> (PAD) +Delay: 7.532ns (Levels of Logic = 5) + Source: Y<4> (PAD) Destination: isNan (PAD) - Data Path: Y<8> to isNan + Data Path: Y<4> to isNan Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF) - LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35) - LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41) - LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61) - LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6) - LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF) - OBUF:I->O 4.909 isNan_OBUF (isNan) + IBUF:I->O 1 1.222 0.944 Y_4_IBUF (Y_4_IBUF) + LUT6:I0->O 1 0.203 0.924 NC/isNan11 (NC/isNan10) + LUT6:I1->O 1 0.203 0.684 NC/isNan12 (NC/isNan11) + LUT6:I4->O 1 0.203 0.579 NC/isNan13 (isNan_OBUF) + OBUF:I->O 2.571 isNan_OBUF (isNan) ---------------------------------------- - Total 13.307ns (8.019ns logic, 5.288ns route) - (60.3% logic, 39.7% route) + Total 7.532ns (4.402ns logic, 3.130ns route) + (58.4% logic, 41.6% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- ========================================================================= -Total REAL time to Xst completion: 3.00 secs -Total CPU time to Xst completion: 3.05 secs +Total REAL time to Xst completion: 22.00 secs +Total CPU time to Xst completion: 19.75 secs --> -Total memory usage is 606300 kilobytes +Total memory usage is 473740 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd index f74787a..4a81344 100644 --- a/SpecialCasesCheck.vhd +++ b/SpecialCasesCheck.vhd @@ -10,33 +10,26 @@ end SpecialCasesCheck; architecture SpecialCasesCheckArch of SpecialCasesCheck is - component TypeCheck is + component NaNCheck is port( - N: in std_logic_vector(31 downto 0); - NaN, INF: out std_logic + X, Y: in std_logic_vector(31 downto 0); + isNan: out std_logic ); end component; - - signal xNan: std_logic; - signal xInf: std_logic; + signal xSign: std_logic; - signal yNan: std_logic; - signal yInf: std_logic; signal ySign: std_logic; signal isSameAbsValue: std_logic; begin - xCheck: TypeCheck - port map (N => X, NaN => xNan, INF => xInf); - yCheck: TypeCheck - port map (N => Y, NaN => yNan, INF => yInf); + NC: NaNCheck + port map (X => X, Y => Y, isNan => isNan); xSign <= X(31); ySign <= Y(31); isSameAbsValue <= '0'; -- TODO - isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign); isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue); end SpecialCasesCheckArch; diff --git a/SpecialCasesCheck.xst b/SpecialCasesCheck.xst index 4ad8c20..b60d7e8 100644 --- a/SpecialCasesCheck.xst +++ b/SpecialCasesCheck.xst @@ -2,13 +2,13 @@ set -tmpdir "xst/projnav.tmp" set -xsthdpdir "xst" run -ifn SpecialCasesCheck.prj --ifmt mixed -ofn SpecialCasesCheck -ofmt NGC --p xc3s50-5-pq208 +-p xa6slx4-3-csg225 -top SpecialCasesCheck -opt_mode Speed -opt_level 1 +-power NO -iuc NO -keep_hierarchy No -netlist_hierarchy As_Optimized @@ -22,31 +22,27 @@ run -case Maintain -slice_utilization_ratio 100 -bram_utilization_ratio 100 --verilog2001 YES +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style LUT -ram_extract Yes -ram_style Auto -rom_extract Yes --mux_style Auto --decoder_extract YES --priority_extract Yes -shreg_extract YES --shift_extract YES --xor_collapse YES -rom_style Auto -auto_bram_packing NO --mux_extract Yes -resource_sharing YES -async_to_sync NO --mult_style Auto +-shreg_min_size 2 +-use_dsp48 Auto -iobuf YES --max_fanout 500 --bufg 8 +-max_fanout 100000 +-bufg 32 -register_duplication YES -register_balancing No --slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes diff --git a/SpecialCasesCheck_envsettings.html b/SpecialCasesCheck_envsettings.html index a9b7595..1d78746 100644 --- a/SpecialCasesCheck_envsettings.html +++ b/SpecialCasesCheck_envsettings.html @@ -15,14 +15,21 @@ LD_LIBRARY_PATH -/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64 +/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64 +< data not available > +< data not available > +< data not available > + + +LMC_HOME +/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64 < data not available > < data not available > < data not available > PATH -/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/Luca/bin +/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
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/usr/sbin:
/sbin:
/home/ise/bin < data not available > < data not available > < data not available > @@ -74,12 +81,6 @@   --ifmt -  -mixed -MIXED - - -ofn   SpecialCasesCheck @@ -94,7 +95,7 @@ -p   -xc3s50-5-pq208 +xa6slx4-3-csg225   @@ -107,7 +108,7 @@ -opt_mode Optimization Goal Speed -SPEED +Speed -opt_level @@ -116,52 +117,58 @@ 1 +-power +Power Reduction +NO +No + + -iuc Use synthesis Constraints File NO -NO +No -keep_hierarchy Keep Hierarchy No -NO +No -netlist_hierarchy Netlist Hierarchy As_Optimized -as_optimized +As_Optimized -rtlview Generate RTL Schematic Yes -NO +No -glob_opt Global Optimization Goal AllClockNets -ALLCLOCKNETS +AllClockNets -read_cores Read Cores YES -YES +Yes -write_timing_constraints Write Timing Constraints NO -NO +No -cross_clock_analysis Cross Clock Analysis NO -NO +No -bus_delimiter @@ -173,37 +180,43 @@ -slice_utilization_ratio Slice Utilization Ratio 100 -100% +100 -bram_utilization_ratio BRAM Utilization Ratio 100 -100% +100 --verilog2001 -Verilog 2001 -YES -YES +-dsp_utilization_ratio +DSP Utilization Ratio +100 +100 + + +-reduce_control_sets +  +Auto +Auto -fsm_extract   YES -YES +Yes -fsm_encoding   Auto -AUTO +Auto -safe_implementation   No -NO +No -fsm_style @@ -215,127 +228,127 @@ -ram_extract   Yes -YES +Yes -ram_style   Auto -AUTO +Auto -rom_extract   Yes -YES +Yes -shreg_extract   YES -YES +Yes -rom_style   Auto -AUTO +Auto -auto_bram_packing   NO -NO +No -resource_sharing   YES -YES +Yes -async_to_sync   NO -NO +No --mult_style +-use_dsp48   Auto -AUTO +Auto -iobuf   YES -YES +Yes -max_fanout   -500 -500 +100000 +100000 -bufg   -8 -8 +32 +16 -register_duplication   YES -YES +Yes -register_balancing   No -NO +No -optimize_primitives   NO -NO +No -use_clock_enable   Yes -YES +Auto -use_sync_set   Yes -YES +Auto -use_sync_reset   Yes -YES +Auto -iob   Auto -AUTO +Auto -equivalent_register_removal   YES -YES +Yes -slice_utilization_ratio_maxmargin   5 -0% +0 @@ -352,28 +365,28 @@ CPU Architecture/Speed -Intel Core Processor (Haswell, no TSX)/2494.222 MHz +Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz <  data not available  > <  data not available  > <  data not available  > Host -Xilinx +localhost.localdomain <  data not available  > <  data not available  > <  data not available  > OS Name -CentOS +OracleServer <  data not available  > <  data not available  > <  data not available  > OS Release -CentOS release 6.10 (Final) +Oracle Linux Server release 6.4 <  data not available  > <  data not available  > <  data not available  > diff --git a/SpecialCasesCheck_summary.html b/SpecialCasesCheck_summary.html index cc69285..c575689 100644 --- a/SpecialCasesCheck_summary.html +++ b/SpecialCasesCheck_summary.html @@ -2,7 +2,7 @@ - + @@ -17,14 +17,15 @@ - + - + - + @@ -42,7 +43,7 @@ @@ -52,7 +53,26 @@ System Settings - + 
SpecialCasesCheck Project Status (08/17/2019 - 16:41:04)
SpecialCasesCheck Project Status (08/17/2019 - 17:19:45)
Project File: IEEE754Adder.xise
Target Device:xc3s50-5pq208xa6slx4-3csg225
  • Errors:
  +No Errors
Product Version:ISE 14.7
  • Warnings:
 1 Warning (1 new)
Design Goal:
Environment: - + System Settings
  • Final Timing Score:
+ + + + + + + + + + + + + + + + + + +
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs1524000%
Number of fully used LUT-FF pairs0150%
Number of bonded IOBs6613250%
@@ -64,7 +84,7 @@ System Settings Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentSat Aug 17 16:39:00 2019    +Synthesis ReportCurrentSat Aug 17 17:19:45 201901 Warning (1 new)0 Translation Report      Map Report      Place and Route Report      @@ -78,5 +98,5 @@ System Settings -
Date Generated: 08/17/2019 - 16:41:04
+
Date Generated: 08/17/2019 - 17:19:45
\ No newline at end of file diff --git a/SpecialCasesCheck_xst.xrpt b/SpecialCasesCheck_xst.xrpt index 2217582..93a37c7 100644 --- a/SpecialCasesCheck_xst.xrpt +++ b/SpecialCasesCheck_xst.xrpt @@ -5,7 +5,7 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
@@ -16,7 +16,7 @@ - + @@ -24,98 +24,86 @@ - + + + + + - +
- - + + - + - - - - - - - - - - - - - - + +
- - + - + - - - - - - - - + + + + + + + + + - - - - - - - + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + +
@@ -124,23 +112,17 @@
-
-
- - - - - +
+
+
-
- -
-
- +
+ - - + + + @@ -149,11 +131,16 @@
- - - + + + + + + + + - +
diff --git a/TypeCheck_envsettings.html b/TypeCheck_envsettings.html new file mode 100644 index 0000000..cac681c --- /dev/null +++ b/TypeCheck_envsettings.html @@ -0,0 +1,509 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64		/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64		/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64		/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64
LMC_HOME/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64<  not set  ><  not set  ><  not set  >
PATH/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/ise/bin		/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/Luca/bin		/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/Luca/bin		/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/Luca/bin
XILINX/opt/Xilinx/14.7/ISE_DS/ISE//opt/Xilinx/14.7/ISE_DS/ISE//opt/Xilinx/14.7/ISE_DS/ISE//opt/Xilinx/14.7/ISE_DS/ISE/
XILINX_DSP/opt/Xilinx/14.7/ISE_DS/ISE/opt/Xilinx/14.7/ISE_DS/ISE/opt/Xilinx/14.7/ISE_DS/ISE/opt/Xilinx/14.7/ISE_DS/ISE
XILINX_EDK/opt/Xilinx/14.7/ISE_DS/EDK/opt/Xilinx/14.7/ISE_DS/EDK/opt/Xilinx/14.7/ISE_DS/EDK/opt/Xilinx/14.7/ISE_DS/EDK
XILINX_PLANAHEAD/opt/Xilinx/14.7/ISE_DS/PlanAhead/opt/Xilinx/14.7/ISE_DS/PlanAhead/opt/Xilinx/14.7/ISE_DS/PlanAhead/opt/Xilinx/14.7/ISE_DS/PlanAhead
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn TypeCheck.prj 
-ofn TypeCheck 
-ofmt NGCNGC
-p xa6slx4-3-csg225 
-top TypeCheck 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 3216
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable YesAuto
-use_sync_set YesAuto
-use_sync_reset YesAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc3s50-pq208-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Map Property Settings
Switch NameProperty NameValueDefault Value
-irUse RLOC ConstraintsOFFOFF
-cmOptimization Strategy (Cover Mode)areaarea
-intstyle iseNone
-o TypeCheck_map.ncdNone
-prPack I/O Registers/Latches into IOBsoffoff
-p xc3s50-pq208-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-t 11
-intstyle ise 
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHzIntel Core Processor (Haswell, no TSX)/2494.222 MHzIntel Core Processor (Haswell, no TSX)/2494.222 MHzIntel Core Processor (Haswell, no TSX)/2494.222 MHz
Hostlocalhost.localdomainXilinxXilinxXilinx
OS NameOracleServerCentOSCentOSCentOS
OS ReleaseOracle Linux Server release 6.4CentOS release 6.10 (Final)CentOS release 6.10 (Final)CentOS release 6.10 (Final)
+ \ No newline at end of file diff --git a/TypeCheck_summary.html b/TypeCheck_summary.html new file mode 100644 index 0000000..bbadc90 --- /dev/null +++ b/TypeCheck_summary.html @@ -0,0 +1,102 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeCheck Project Status (08/17/2019 - 16:39:36)
Project File:IEEE754Adder.xiseParser Errors: No Errors
Module Name:TypeCheckImplementation State:Synthesized
Target Device:xa6slx4-3csg225
  • Errors:
 +No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (1 new)
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
  
+ + + + 
+ + + + + + + + + + + + + + + + + + +
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs924000%
Number of fully used LUT-FF pairs090%
Number of bonded IOBs3313225%
+ + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentSat Aug 17 16:39:35 201901 Warning (1 new)0
Translation ReportOut of DateSat Aug 17 16:35:26 2019000
Map ReportOut of DateSat Aug 17 16:35:26 2019004 Infos (0 new)
Place and Route ReportOut of DateSat Aug 17 16:35:26 2019001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportOut of DateSat Aug 17 16:35:26 2019006 Infos (0 new)
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 08/17/2019 - 16:39:36
+ \ No newline at end of file diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index c57b568..2aee04b 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work +Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs index 7f18513..71eed22 100644 --- a/_xmsgs/xst.xmsgs +++ b/_xmsgs/xst.xmsgs @@ -5,7 +5,7 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +Input <N<31:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. diff --git a/iseconfig/IEEE754Adder.projectmgr b/iseconfig/IEEE754Adder.projectmgr new file mode 100644 index 0000000..0b2671e --- /dev/null +++ b/iseconfig/IEEE754Adder.projectmgr @@ -0,0 +1,76 @@ + + + + + + + + + 2 + + + SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000222000000020000000000000000000000000200000064ffffffff000000810000000300000002000002220000000100000003000000000000000100000003 + true + SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd) + + + + 1 + Configure Target Device + Design Utilities + Implement Design + User Constraints + + + View RTL Schematic + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000 + false + View RTL Schematic + + + + 1 + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000028a000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b600000001000000000000005d0000000100000000000000840000000100000000000000f30000000100000000 + false + SpecialCasesCheck.vhd + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000 + false + work + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000 + false + + + 000000ff00000000000000020000014c0000011d01000000060100000002 + Implementation + diff --git a/iseconfig/SpecialCasesCheck.xreport b/iseconfig/SpecialCasesCheck.xreport index 0aa7809..3623fdb 100644 --- a/iseconfig/SpecialCasesCheck.xreport +++ b/iseconfig/SpecialCasesCheck.xreport @@ -1,11 +1,11 @@
- 2019-08-17T15:26:24 + 2019-08-17T16:51:16 SpecialCasesCheck Unknown - /home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport - /home/Luca/ISE/IEEE754Adder + /home/ise/gianni/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport + /home/ise/gianni/IEEE754Adder/ 2019-08-17T15:26:24 false
diff --git a/iseconfig/TypeCheck.xreport b/iseconfig/TypeCheck.xreport new file mode 100644 index 0000000..5ff9ff0 --- /dev/null +++ b/iseconfig/TypeCheck.xreport @@ -0,0 +1,215 @@ + + +
+ 2019-08-17T16:37:54 + TypeCheck + Unknown + /home/ise/gianni/IEEE754Adder/iseconfig/TypeCheck.xreport + /home/ise/gianni/IEEE754Adder + 2019-08-17T16:37:53 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/webtalk_pn.xml b/webtalk_pn.xml index b32f26a..e8c38e2 100644 --- a/webtalk_pn.xml +++ b/webtalk_pn.xml @@ -3,15 +3,16 @@ - +
- + - - + +
+ @@ -21,19 +22,26 @@ This means code written to parse this file will need to be revisited each subseq - - - - + + + + + + + + + + + - - - - + + + + - + - +
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