56 lines
1.1 KiB
VHDL
56 lines
1.1 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity SumDataAdapter is
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port(
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X_IN, Y_IN : in std_logic_vector(30 downto 0);
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DIFF_EXP : in std_logic_vector(8 downto 0);
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X_OUT, Y_OUT : out std_logic_vector(47 downto 0)
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);
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end SumDataAdapter;
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architecture SumDataAdapterArch of SumDataAdapter is
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signal X_FST_BIT : std_logic;
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signal Y_FST_BIT : std_logic;
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component ShiftRight48 is
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port(
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N : in std_logic_vector(47 downto 0);
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PLACES : in std_logic_vector(8 downto 0);
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RESULT : out std_logic_vector(47 downto 0)
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);
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end component;
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begin
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X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
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variable X_FST_TMP : std_logic := '0';
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variable Y_FST_TMP : std_logic := '0';
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begin
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for i in 30 downto 23 loop
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X_FST_TMP := X_FST_TMP or X_IN(i);
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Y_FST_TMP := Y_FST_TMP or Y_IN(i);
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end loop;
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X_FST_BIT <= X_FST_TMP;
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Y_FST_BIT <= Y_FST_TMP;
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end process;
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--istanziare shifter
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SHIFTER : ShiftRight48
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port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT);
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X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000";
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end SumDataAdapterArch;
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