IEEE754Adder/isim/SwapTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg

<EFBFBD>
<0A><>y(e]<5D><><EFBFBD><EFBFBD><EFBFBD>D
<00>@@@@8<00>`
`
<00><00><00><00>

!<00><00>	<00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>	<00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
$
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>4
 9
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>I
!O
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>
<00><0E><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>

<00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>c
"
I
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>s
#
I

<00><><EFBFBD><EFBFBD>
$I
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>
%I

<00><><EFBFBD><EFBFBD><00>
&
I
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>
'
I

<00><><EFBFBD><EFBFBD><00>
(
I
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>
)
	I

<00><><EFBFBD><EFBFBD><00>
*

I
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>+
I

<00><><EFBFBD><EFBFBD>p
<00><><EFBFBD><EFBFBD>
<00><><EFBFBD><EFBFBD>b
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>g<00><><EFBFBD><EFBFBD>;Lz8<00><><EFBFBD><EFBFBD>4<00><><EFBFBD><EFBFBD>
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><10>ȸ$-5<10>ȸ<EFBFBD><00><00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>
%
%
%<@E?


+ x<00>w=

<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>444 <00><00>w>

<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>>>> <00><00>K
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>66

;7


@8
<00><><EFBFBD><EFBFBD>C9

 I:

	!O;
<00><><EFBFBD><EFBFBD>"<10>ȸU<
<00><><EFBFBD><EFBFBD>& <00>,
<00> <00>-<00> <00>.<00> /<00> 0

 1
6 $2
M 03
d<00>z<EFBFBD>N@

<00>z<EFBFBD>SB

<00>z<EFBFBD>XD<00><><EFBFBD><EFBFBD>
<00>z<EFBFBD>[F
	<00>z<EFBFBD>aH
	gJ <00><><EFBFBD><EFBFBD>
  










%
%
%
%
#
'
	)
+









<10>ȸ	<10>ȸ	<10>ȸ	<10>ȸ	<10>ȸ	<10>ȸ	
<1C>ȸ<1C>ȸ<1C>ȸ<00><18>	<00><18>	<00><18>	<00><18>	<1C>ȸ	<1C>ȸ	<1C>ȸ	<1C>ȸ	<1C>ȸ	<1C>ȸ	<1C>ȸ	<1C>ȸ	p<1F>p<1F><00><>ȸ<00><>ȸ










	



+h<00>
<00>@Bʚ;<10><><EFBFBD><00>Ƥ~<7E><00>]xEc
d<><64><EFBFBD><EFBFBD>
/home/ise/gianni/IEEE754Adder/SwapTest.vhd/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee/std_logic_1164.vhd/home/ise/gianni/IEEE754Adder/Swap.vhdstd_ulogic'U''X''0''1''Z''W''L''H''-'std_ulogic_vectorstd_logic'U''X''0''1''Z''W''L''H''-'std_logic_vectorx01'X''0''1'x01z'X''0''1''Z'ux01'U''X''0''1'ux01z'U''X''0''1''Z'stdlogic_1dBasestdlogic_1dstdlogic_tableBasestdlogic_tablelogic_x01_tableBaselogic_x01_tablelogic_x01z_tableBaselogic_x01z_tablelogic_ux01_tableBaselogic_ux01_table_top_topswaptestswaptestbehaviorx_iny_inswx_outy_outclockclock_periodtimefspsnsusmssecminhrstd_logic_1164std_logic_1164resolution_table/build/legacysi10/P.20160913/rtf/vhdl/src/ieee/std_logic_1164.vhdand_tableor_tablexor_tablenot_tablecvt_to_x01cvt_to_x01zcvt_to_ux01uutSwapSwapArchx_iny_inswx_outy_outbitcountinteger:clock_processswaptest:stim_procswaptest:SWAP_PROSwap