Files
IEEE754Adder/isim/SpecialCasesTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg

44 lines
9.6 KiB
Plaintext
Raw Normal View History

2019-08-28 21:50:05 +02:00
<EFBFBD> <0A><><EFBFBD>4a]<5D><><EFBFBD><EFBFBD><EFBFBD>D<00>@@@@ <00>pp<00>E&<00>`<00> #?K%<00>H S<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00> <00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00><00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00><00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00> <00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>!<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>w@y<><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00><00><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>"<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,#<00><><EFBFBD><EFBFBD>8$<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>K%<00><><EFBFBD><EFBFBD>Z&<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n'<00><><EFBFBD><EFBFBD>~(<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>) <00><><EFBFBD><EFBFBD><00>*
<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00>+ <00><><EFBFBD><EFBFBD><00> <00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>B<00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>G<00><><EFBFBD><EFBFBD>:L:9<><39><00><00><><EFBFBD><EFBFBD>4<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><>=]<5D><00><00>5 <00><>=]ap<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD> %%%0B * Wfh?
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>222 w<00>h@
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>;;; <00><00>hA
2019-08-24 14:39:01 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><00><00><00><00><00>K  <00><00><00><00>  PELV[' P~<00><00>n.  <00><00>X
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>   <00><00>Y
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>!!! <00><00>Z
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>###`<60>=]<5D><00>hh
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>`<60>=]<5D><00>hi
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>`<60>=]<5D>hj
<00><><EFBFBD><EFBFBD>5`<60>=] hk
<00><><EFBFBD><EFBFBD>6`<60>=]04hl
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>(((`<60>=]>Bhm
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>)))`<60>=]LPh{
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>`<60>=]Z^h|
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>`<60>=]hsh}
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD>7`<60>=]<5D><00>h~
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD>8`<60>=]<5D><00>h
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>(((`<60>=]<5D><00>h<00>
2019-08-24 14:39:01 +02:00
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>)))<00><>=]<5D><00><00><00>!9 "<00><>=]h<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><>=]h<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><>=]"h<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><>=],0h<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD><00><>=]:>h<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>!!!<00><>=]HLh<00>
2019-08-24 14:39:01 +02:00
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD>&&& VZ<00>
<00><><EFBFBD><EFBFBD><00><><EFBFBD><EFBFBD> er<00>
2019-08-28 21:50:05 +02:00
<00><><EFBFBD><EFBFBD>><00>6  7  8<00><><EFBFBD><EFBFBD>  9<00><><EFBFBD><EFBFBD> :<00><><EFBFBD><EFBFBD> ;<00><><EFBFBD><EFBFBD> !"<<00><><EFBFBD><EFBFBD> "/=<00><><EFBFBD><EFBFBD> #<00><>=]5><00><><EFBFBD><EFBFBD>% ,<00> <00>-
<00> <00>. <00> <00>/<00> <00>0 <00>16 2M 3dFC HE JG<00><><EFBFBD><EFBFBD> PI <00><><EFBFBD><EFBFBD> 0<><30><01>L! 0<><30><01>N" 0<><30><01>P#<00><><EFBFBD><EFBFBD> 0<><30><01>R$<00><><EFBFBD><EFBFBD> 0<><30><01>S%<00><><EFBFBD><EFBFBD> 0<><30><01>T&<00><><EFBFBD><EFBFBD> 0<><30><01>U'<00><><EFBFBD><EFBFBD> 0<><30><01>V(<00><><EFBFBD><EFBFBD> 0<><30><01>W)<00><><EFBFBD><EFBFBD>  <20><>
<00>*  <20><> <00>+  <20><><00>,<00><><EFBFBD><EFBFBD>  <20><><00>-<00><><EFBFBD><EFBFBD>  <20><><00>.<00><><EFBFBD><EFBFBD>  <20><>!<00>/  <20><>&<00>0  <20><>+<00>1<00><><EFBFBD><EFBFBD>  <20><>:<00>2<00><><EFBFBD><EFBFBD> <00>/<2F>d\ 3 <00>/<2F>f^ 4<00><><EFBFBD><EFBFBD> <00>/<2F>j` 5<00><><EFBFBD><EFBFBD> <00>/<2F>nb 6  <00>/<2F>tc 7  <00>/<2F>zd 8<00><><EFBFBD><EFBFBD> <00>/<2F>|e 9<00><><EFBFBD><EFBFBD> <10><><01>o
: <10><><01>q
;<00><><EFBFBD><EFBFBD> <10><><01>s
<<00><><EFBFBD><EFBFBD> <10><><01>u
=  <10><><01>v
>!  <10><><01>w
?<00><><EFBFBD><EFBFBD> <10><><01>x
@<00><><EFBFBD><EFBFBD> @fA<00><><EFBFBD><EFBFBD> 0<><30>*gB<00><><EFBFBD><EFBFBD> @}yC<00><><EFBFBD><EFBFBD> @<00>zD<00><><EFBFBD><EFBFBD> <00><00>E" <00><00>F# <00><00>G<00><><EFBFBD><EFBFBD> <00><00>H$  H<00><00>I<00><><EFBFBD><EFBFBD>@}<00>"J<00><><EFBFBD><EFBFBD>   %%%%#' ) + <00><>=] <00><>=] <00><>=] <00><>=] <00><>=] <00><>=]  <00><>=] <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD>      <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><><EFBFBD> <00><>=]<00><>=]<00><><EFBFBD> <00><><EFBFBD><00><><EFBFBD><00><><EFBFBD> <00><><EFBFBD><00><><EFBFBD>))) 
2019-08-24 14:39:01 +02:00
 1n<00><00><00><00><00>@Bʚ;<10><><EFBFBD><00>Ƥ~<7E><00>]xEcd<><64><EFBFBD><EFBFBD> /home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ieee/std_logic_1164.vhd/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd/home/Luca/ISE/IEEE754Adder/EqualCheck.vhdstd_ulogic'U''X''0''1''Z''W''L''H''-'std_ulogic_vectorstd_logic'U''X''0''1''Z''W''L''H''-'std_logic_vectorx01'X''0''1'x01z'X''0''1''Z'ux01'U''X''0''1'ux01z'U''X''0''1''Z'stdlogic_1dBasestdlogic_1dstdlogic_tableBasestdlogic_tablelogic_x01_tableBaselogic_x01_tablelogic_x01z_tableBaselogic_x01z_tablelogic_ux01_tableBaselogic_ux01_table_top_topspecialcasestestspecialcasestestbehaviorxyisnaniszeroclockexpectednanexpectedzeroerrorclock_periodtimefspsnsusmssecminhrstd_logic_1164std_logic_1164resolution_table/build/xfndry10/P.20131013/rtf/vhdl/src/ieee/std_logic_1164.vhdand_tableor_tablexor_tablenot_tablecvt_to_x01cvt_to_x01zcvt_to_ux01uutSpecialCasesCheckSpecialCasesCheckArchxyisnaniszero:clock_processspecialcasestest:test_processspecialcasestest:163specialcasestestNCNaNCheckNaNCheckArchxyisnanxnanxinfxsignynanyinfysignZCZeroCheckZeroCheckArchxyiszeroxsignysignxabsyabsissameabsvalueissamesignxCheckTypeCheckTypeCheckArchnnaninfg_bust_busgtyCheckTypeCheckTypeCheckArchnnaninfg_bust_busgt:32NaNCheck:33NaNCheck:35NaNCheck:17TypeCheck:18TypeCheck:G_computeTypeCheckg_tmp:T_computeTypeCheckt_tmp:40TypeCheck:41TypeCheck:17TypeCheck:18TypeCheck:G_computeTypeCheckg_tmp:T_computeTypeCheckt_tmp:40TypeCheck:41TypeCheckAbsCheckEqualCheckEqualCheckArchxyisequalcompvecbitcountinteger:28ZeroCheck:29ZeroCheck:30ZeroCheck:31ZeroCheck:33ZeroCheck:38ZeroCheck:15EqualCheck:res_computeEqualCheckres_tmp