66 lines
1.3 KiB
VHDL
66 lines
1.3 KiB
VHDL
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY ComparatorTest IS
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END ComparatorTest;
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ARCHITECTURE behavior OF ComparatorTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Comparator
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PORT(
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xT : IN std_logic_vector(7 downto 0);
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yT : IN std_logic_vector(7 downto 0);
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needSwap : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal xT : std_logic_vector(7 downto 0) := "11111111";
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signal yT : std_logic_vector(7 downto 0) := "11111111";
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--Outputs
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signal needSwap : std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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signal clock: std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Comparator PORT MAP (
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xT => xT,
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yT => yT,
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needSwap => needSwap
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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wait for clock_period*10;
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-- insert stimulus here
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wait;
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end process;
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END;
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