60 lines
1.1 KiB
VHDL
60 lines
1.1 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity TypeCheck is
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port(
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N: in std_logic_vector(31 downto 0);
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NaN, INF: out std_logic
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);
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end TypeCheck;
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architecture TypeCheckArch of TypeCheck is
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signal G_Bus: std_logic_vector(7 downto 0);
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signal T_Bus: std_logic_vector(22 downto 0);
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signal G: std_logic := '1';
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signal T: std_logic := '0';
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begin
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G_Bus <= N(30 downto 23);
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T_Bus <= N(22 downto 0);
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G_compute: process (G_Bus)
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variable G_tmp: std_logic;
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begin
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G_tmp := '1';
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for i in G_Bus'range loop
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G_tmp := G_tmp and G_Bus(i);
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end loop;
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G <= G_tmp;
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end process;
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T_compute: process (T_Bus)
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variable T_tmp: std_logic;
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begin
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T_tmp := '0';
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for i in T_Bus'range loop
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T_tmp := T_tmp or T_Bus(i);
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end loop;
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T <= T_tmp;
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end process;
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NaN <= G and T;
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INF <= G and (not T);
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end TypeCheckArch;
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--entity SpecialCasesCheck is
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-- port(
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-- X, Y: in std_logic_vector(31 downto 0);
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-- isNan, isZero: out std_logic
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-- );
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--end SpecialCasesCheck;
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--
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--
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--architecture SpecialCasesCheckArch of SpecialCasesCheck is
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--
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--begin
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--
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--end SpecialCasesCheckArch;
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