39 lines
781 B
VHDL
39 lines
781 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity NaNCheck is
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port(
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X, Y: in std_logic_vector(31 downto 0);
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isNan: out std_logic
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);
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end NaNCheck;
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architecture NaNCheckArch of NaNCheck is
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component TypeCheck is
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port(
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N: in std_logic_vector(31 downto 0);
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NaN, INF: out std_logic
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);
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end component;
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signal xNan: std_logic;
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signal xInf: std_logic;
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signal xSign: std_logic;
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signal yNan: std_logic;
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signal yInf: std_logic;
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signal ySign: std_logic;
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begin
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xCheck: TypeCheck
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port map (N => X, NaN => xNan, INF => xInf);
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yCheck: TypeCheck
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port map (N => Y, NaN => yNan, INF => yInf);
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xSign <= X(31);
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ySign <= Y(31);
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isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
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end NaNCheckArch;
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