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< HTML >< HEAD >< TITLE > Xilinx Design Summary</ TITLE ></ HEAD >
< BODY TEXT = '#000000' BGCOLOR = '#FFFFFF' LINK = '#0000EE' VLINK = '#551A8B' ALINK = '#FF0000' >
< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >
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< TD ALIGN = CENTER COLSPAN = '4' >< B > SpecialCasesCheck Project Status (08/24/2019 - 12:14:34)</ B ></ TD ></ TR >
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< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Project File:</ B ></ TD >
< TD > IEEE754Adder.xise</ TD >
< TD BGCOLOR = '#FFFF99' >< b > Parser Errors:</ b ></ TD >
< TD > No Errors </ TD >
</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Module Name:</ B ></ TD >
< TD > SpecialCasesCheck</ TD >
< TD BGCOLOR = '#FFFF99' >< B > Implementation State:</ B ></ TD >
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< TD > Placed and Routed</ TD >
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</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Target Device:</ B ></ TD >
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< TD > xa6slx4-3csg225</ TD >
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< TD BGCOLOR = '#FFFF99' >< UL >< LI >< B > Errors:</ B ></ LI ></ UL ></ TD >
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< TD >
No Errors</ TD >
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</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Product Version:</ B ></ TD >< TD > ISE 14.7</ TD >
< TD BGCOLOR = '#FFFF99' >< UL >< LI >< B > Warnings:</ B ></ LI ></ UL ></ TD >
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< TD ALIGN = LEFT >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning' > 1 Warning (0 new)</ A ></ TD >
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</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Design Goal:</ B ></ dif ></ TD >
< TD > Balanced</ TD >
< TD BGCOLOR = '#FFFF99' >< UL >< LI >< B > Routing Results:</ B ></ LI ></ UL ></ TD >
< TD >
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< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.unroutes' > All Signals Completely Routed</ A ></ TD >
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</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Design Strategy:</ B ></ dif ></ TD >
< TD >< A HREF_DISABLED = 'Xilinx Default (unlocked)?&DataKey=Strategy' > Xilinx Default (unlocked)</ A ></ TD >
< TD BGCOLOR = '#FFFF99' >< UL >< LI >< B > Timing Constraints:</ B ></ LI ></ UL ></ TD >
< TD > </ TD >
</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Environment:</ B ></ dif ></ TD >
< TD >
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< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_envsettings.html' >
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System Settings</ A >
</ TD >
< TD BGCOLOR = '#FFFF99' >< UL >< LI >< B > Final Timing Score:</ B ></ LI ></ UL ></ TD >
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< TD > 0 < A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx?&DataKey=XmlTimingReport' > (Timing Report)</ A ></ TD >
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</ TR >
</ TABLE >
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< BR >< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
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< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >< TD ALIGN = CENTER COLSPAN = '5' >< B > Device Utilization Summary</ B ></ TD >< TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=DeviceUtilizationSummary" >< B > [-]</ B ></ a ></ TD ></ TR >
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< TR ALIGN = CENTER BGCOLOR = '#FFFF99' >
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< TD ALIGN = LEFT >< B > Slice Logic Utilization</ B ></ TD >< TD >< B > Used</ B ></ TD >< TD >< B > Available</ B ></ TD >< TD >< B > Utilization</ B ></ TD >< TD COLSPAN = '2' >< B > Note(s)</ B ></ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of Slice Registers</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 4,800</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
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< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of Slice LUTs</ TD >
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< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 2,400</ TD >
< TD ALIGN = RIGHT > 1%</ TD >
< TD COLSPAN = '2' > </ TD >
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</ TR >
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< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number used as logic</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 2,400</ TD >
< TD ALIGN = RIGHT > 1%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number using O6 output only</ TD >
< TD ALIGN = RIGHT > 25</ TD >
< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number using O5 output only</ TD >
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< TD ALIGN = RIGHT > 0</ TD >
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< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
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</ TR >
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< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number using O5 and O6</ TD >
< TD ALIGN = RIGHT > 1</ TD >
< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number used as ROM</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number used as Memory</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 1,200</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of occupied Slices</ TD >
< TD ALIGN = RIGHT > 10</ TD >
< TD ALIGN = RIGHT > 600</ TD >
< TD ALIGN = RIGHT > 1%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of MUXCYs used</ TD >
< TD ALIGN = RIGHT > 12</ TD >
< TD ALIGN = RIGHT > 1,200</ TD >
< TD ALIGN = RIGHT > 1%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of LUT Flip Flop pairs used</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number with an unused Flip Flop</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 100%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number with an unused LUT</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of fully used LUT-FF pairs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 26</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of slice register sites lost< BR > to control set restrictions</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 4,800</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of bonded < A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_map.xrpt?&DataKey=IOBProperties' > IOBs</ A ></ TD >
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< TD ALIGN = RIGHT > 66</ TD >
< TD ALIGN = RIGHT > 132</ TD >
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< TD ALIGN = RIGHT > 50%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of RAMB16BWERs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 12</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of RAMB8BWERs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 24</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFIO2/BUFIO2_2CLKs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 32</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFIO2FB/BUFIO2FB_2CLKs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 32</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFG/BUFGMUXs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 16</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of DCM/DCM_CLKGENs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 4</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of ILOGIC2/ISERDES2s</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 200</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of IODELAY2/IODRP2/IODRP2_MCBs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 200</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of OLOGIC2/OSERDES2s</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 200</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BSCANs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 4</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFHs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 128</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFPLLs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 8</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of BUFPLL_MCBs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 4</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of DSP48A1s</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 8</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of ICAPs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 1</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of PCILOGICSEs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 2</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of PLL_ADVs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 2</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of PMVs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 1</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of STARTUPs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 1</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Number of SUSPEND_SYNCs</ TD >
< TD ALIGN = RIGHT > 0</ TD >
< TD ALIGN = RIGHT > 1</ TD >
< TD ALIGN = RIGHT > 0%</ TD >
< TD COLSPAN = '2' > </ TD >
</ TR >
< TR ALIGN = RIGHT >< TD ALIGN = LEFT > Average Fanout of Non-Clock Nets</ TD >
< TD ALIGN = RIGHT > 1.78</ TD >
< TD > </ TD >
< TD > </ TD >
< TD COLSPAN = '2' > </ TD >
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</ TR >
</ TABLE >
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< BR >< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >< TD ALIGN = CENTER COLSPAN = '4' >< B > Performance Summary</ B ></ TD >< TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=PerformanceSummary" >< B > [-]</ B ></ a ></ TD ></ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Final Timing Score:</ B ></ TD >
< TD > 0 (Setup: 0, Hold: 0)</ TD >
< TD BGCOLOR = '#FFFF99' >< B > Pinout Data:</ B ></ TD >
< TD COLSPAN = '2' >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_par.xrpt?&DataKey=PinoutData' > Pinout Report</ A ></ TD >
</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Routing Results:</ B ></ TD >< TD >
< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.unroutes' > All Signals Completely Routed</ A ></ TD >
< TD BGCOLOR = '#FFFF99' >< B > Clock Data:</ B ></ TD >
< TD COLSPAN = '2' >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_par.xrpt?&DataKey=ClocksData' > Clock Report</ A ></ TD >
</ TR >
< TR ALIGN = LEFT >
< TD BGCOLOR = '#FFFF99' >< B > Timing Constraints:</ B ></ TD >
< TD > </ TD >
< TD BGCOLOR = '#FFFF99' >< B > </ B ></ TD >
< TD COLSPAN = '2' > </ TD >
</ TABLE >
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< BR >< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >< TD ALIGN = CENTER COLSPAN = '6' >< B > Detailed Reports</ B ></ TD >< TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=DetailedReports" >< B > [-]</ B ></ a ></ TD ></ TR >
< TR BGCOLOR = '#FFFF99' >< TD >< B > Report Name</ B ></ TD >< TD >< B > Status</ B ></ TD >< TD >< B > Generated</ B ></ TD >
< TD ALIGN = LEFT >< B > Errors</ B ></ TD >< TD ALIGN = LEFT >< B > Warnings</ B ></ TD >< TD ALIGN = LEFT COLSPAN = '2' >< B > Infos</ B ></ TD ></ TR >
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< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr' > Synthesis Report</ A ></ TD >< TD > Current</ TD >< TD > Sat Aug 24 12:14:14 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning' > 1 Warning (0 new)</ A ></ TD >< TD ALIGN = LEFT COLSPAN = '2' > 0</ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.bld' > Translation Report</ A ></ TD >< TD > Current</ TD >< TD > Sat Aug 24 12:14:17 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT COLSPAN = '2' > 0</ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_map.mrp' > Map Report</ A ></ TD >< TD > Current</ TD >< TD > Sat Aug 24 12:14:25 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT COLSPAN = '2' >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/_xmsgs/map.xmsgs?&DataKey=Info' > 5 Infos (0 new)</ A ></ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.par' > Place and Route Report</ A ></ TD >< TD > Current</ TD >< TD > Sat Aug 24 12:14:30 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT COLSPAN = '2' >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/_xmsgs/par.xmsgs?&DataKey=Info' > 2 Infos (0 new)</ A ></ TD ></ TR >
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< TR ALIGN = LEFT >< TD > Power Report</ TD >< TD > </ TD >< TD > </ TD >< TD > </ TD >< TD > </ TD >< TD COLSPAN = '2' > </ TD ></ TR >
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< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twr' > Post-PAR Static Timing Report</ A ></ TD >< TD > Current</ TD >< TD > Sat Aug 24 12:14:33 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT COLSPAN = '2' >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/_xmsgs/trce.xmsgs?&DataKey=Info' > 4 Infos (0 new)</ A ></ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.bgn' > Bitgen Report</ A ></ TD >< TD > Out of Date</ TD >< TD > Sat Aug 24 10:52:30 2019</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT > 0</ TD >< TD ALIGN = LEFT COLSPAN = '2' > 0</ TD ></ TR >
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</ TABLE >
< BR >< TABLE BORDER CELLSPACING = 0 CELLPADDING = 3 WIDTH = '100%' >
< TR ALIGN = CENTER BGCOLOR = '#99CCFF' >< TD ALIGN = CENTER COLSPAN = '3' >< B > Secondary Reports</ B ></ TD >< TD ALIGN = RIGHT WIDTH = '10%' COLSPAN = 1 > < A HREF_DISABLED = "?&ExpandedTable=SecondaryReports" >< B > [-]</ B ></ a ></ TD ></ TR >
< TR BGCOLOR = '#FFFF99' >< TD >< B > Report Name</ B ></ TD >< TD >< B > Status</ B ></ TD >< TD COLSPAN = '2' >< B > Generated</ B ></ TD ></ TR >
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< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/isim.log' > ISIM Simulator Log</ A ></ TD >< TD > Out of Date</ TD >< TD COLSPAN = '2' > Sat Aug 24 12:12:57 2019</ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/netgen/synthesis/SpecialCasesCheck_synthesis.nlf' > Post-Synthesis Simulation Model Report</ A ></ TD >< TD > Out of Date</ TD >< TD COLSPAN = '2' > Sat Aug 24 10:53:07 2019</ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/usage_statistics_webtalk.html' > WebTalk Report</ A ></ TD >< TD > Out of Date</ TD >< TD COLSPAN = '2' > Sat Aug 24 10:52:31 2019</ TD ></ TR >
< TR ALIGN = LEFT >< TD >< A HREF_DISABLED = '/home/Luca/ISE/IEEE754Adder/webtalk.log' > WebTalk Log File</ A ></ TD >< TD > Out of Date</ TD >< TD COLSPAN = '2' > Sat Aug 24 10:52:32 2019</ TD ></ TR >
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</ TABLE >
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< br >< center >< b > Date Generated:</ b > 08/24/2019 - 12:14:34</ center >
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</ BODY ></ HTML >
