148 lines
6.0 KiB
Plaintext
148 lines
6.0 KiB
Plaintext
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Release 14.7 par P.20131013 (lin64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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Xilinx:: Sat Aug 24 12:14:27 2019
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par -w -intstyle ise -ol high -mt off SpecialCasesCheck_map.ncd
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SpecialCasesCheck.ncd SpecialCasesCheck.pcf
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Constraints file: SpecialCasesCheck.pcf.
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Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
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"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
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Initializing temperature to 100.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
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Device speed data version: "PRODUCTION 1.23 2013-10-13".
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Device Utilization Summary:
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Slice Logic Utilization:
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Number of Slice Registers: 0 out of 4,800 0%
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Number of Slice LUTs: 26 out of 2,400 1%
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Number used as logic: 26 out of 2,400 1%
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Number using O6 output only: 25
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Number using O5 output only: 0
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Number using O5 and O6: 1
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Number used as ROM: 0
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Number used as Memory: 0 out of 1,200 0%
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Slice Logic Distribution:
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Number of occupied Slices: 10 out of 600 1%
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Number of MUXCYs used: 12 out of 1,200 1%
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Number of LUT Flip Flop pairs used: 26
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Number with an unused Flip Flop: 26 out of 26 100%
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Number with an unused LUT: 0 out of 26 0%
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Number of fully used LUT-FF pairs: 0 out of 26 0%
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Number of slice register sites lost
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to control set restrictions: 0 out of 4,800 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 66 out of 132 50%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 12 0%
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Number of RAMB8BWERs: 0 out of 24 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 0 out of 16 0%
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 8 0%
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Number of ICAPs: 0 out of 1 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 2 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Overall effort level (-ol): High
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 2 secs
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Finished initial Timing Analysis. REAL time: 2 secs
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Starting Router
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Phase 1 : 155 unrouted; REAL time: 2 secs
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Phase 2 : 145 unrouted; REAL time: 2 secs
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Phase 3 : 214 unrouted; REAL time: 2 secs
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Phase 4 : 214 unrouted; (Par is working to improve performance) REAL time: 2 secs
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Updating file: SpecialCasesCheck.ncd with current fully routed design.
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 3 secs
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Total REAL time to Router completion: 3 secs
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Total CPU time to Router completion: 3 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
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Timing Score: 0 (Setup: 0, Hold: 0)
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 3 secs
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Total CPU time to PAR completion: 3 secs
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Peak Memory Usage: 596 MB
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Placer: Placement generated during map.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 2
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Writing design to file SpecialCasesCheck.ncd
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PAR done!
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