85 lines
2.3 KiB
VHDL
85 lines
2.3 KiB
VHDL
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY PrepareForShiftTest IS
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END PrepareForShiftTest;
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ARCHITECTURE behavior OF PrepareForShiftTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT PrepareForShift
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PORT(
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X : IN std_logic_vector(30 downto 0);
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Y : IN std_logic_vector(30 downto 0);
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DIFF_EXP : OUT std_logic_vector(8 downto 0);
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NEED_SWAP : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(30 downto 0) := (others => '0');
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signal Y : std_logic_vector(30 downto 0) := (others => '0');
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--Outputs
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signal DIFF_EXP : std_logic_vector(8 downto 0);
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signal NEED_SWAP : std_logic;
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: PrepareForShift PORT MAP (
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X => X,
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Y => Y,
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DIFF_EXP => DIFF_EXP,
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NEED_SWAP => NEED_SWAP
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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X <= "00011100" & "00001110000000000000000";
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Y <= "00100011" & "00100000000000000000000";
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wait for clock_period;
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X <= "00110000" & "00000000111000000000000";
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Y <= "10110000" & "00000001111000000000000";
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wait for clock_period;
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X <= "00001000" & "00000011001100000000000";
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Y <= "00011000" & "00000000100000000001110";
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wait for clock_period;
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X <= "00001100" & "00000000000000000000000";
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Y <= "00001100" & "00000000000000000000000";
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wait for clock_period;
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X <= "00010010" & "00000000011001000100000";
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Y <= "00010010" & "00000010011000000000000";
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wait for clock_period;
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X <= "01011000" & "00000000100000000000000";
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Y <= "01011000" & "00000000000000000000000";
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wait for clock_period;
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X <= "00100110" & "00000000011100001000100";
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Y <= "00001010" & "00000000011100001000100";
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wait for clock_period;
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X <= "01111100" & "00000001110000000101010";
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Y <= "00000100" & "00000101110000100110000";
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wait for clock_period;
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wait for clock_period;
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X <= "00100000" & "00000110000000000000000";
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Y <= "00001000" & "00000000100100100100000";
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wait for clock_period;
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end process;
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END;
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