47 lines
2.3 KiB
Plaintext
47 lines
2.3 KiB
Plaintext
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
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ISim P.20131013 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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Determining compilation order of HDL files
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 94252 KB
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Fuse CPU Usage: 950 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
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Compiling architecture behavior of entity addertest
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Time Resolution for simulation is 1ps.
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 5 VHDL Units
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Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
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Fuse Memory Usage: 657936 KB
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Fuse CPU Usage: 980 ms
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GCC CPU Usage: 140 ms
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=======
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
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ISim P.20160913 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 1
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Turning on mult-threading, number of parallel sub-compilation jobs: 0
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Determining compilation order of HDL files
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 95308 KB
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Fuse CPU Usage: 2530 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture fulladderarch of entity FullAdder [fulladder_default]
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Compiling architecture behavior of entity fulladdertest
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Time Resolution for simulation is 1ps.
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Compiled 5 VHDL Units
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Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe
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Fuse Memory Usage: 103940 KB
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Fuse CPU Usage: 2640 ms
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GCC CPU Usage: 440 ms
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>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
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